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1. 发明授权

US5900675A Organic controlled collapse chip connector (C4) ball grid array (BGA) chip carrier with dual thermal expansion rates 失效
标题翻译：有机控制崩溃芯片连接器（C4）球栅阵列（BGA）芯片载体具有双热膨胀率
公开(公告)号：US5900675A
公开(公告)日：1999-05-04
申请号：US840518
申请日：1997-04-21
申请人： Bernd Karl-Heinz Appelt , Donald Seton Farquhar , Robert Maynard Japp , Konstantinos I. Papathomas
发明人： Bernd Karl-Heinz Appelt , Donald Seton Farquhar , Robert Maynard Japp , Konstantinos I. Papathomas
IPC分类号： H01L23/13 , H01L23/14 , H01L23/48
CPC分类号： H01L23/142 , H01L23/13 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L24/48 , H01L2924/00014 , H01L2924/01039 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/181
摘要： An integrated circuit chip package with an integrated chip carrier having differing coefficients of thermal expansion (CTE) in the x-y plane. The chip carrier is comprised of two main regions. The first is a core region having a CTE approximately equal to that of the semiconductor chip CTE. This core region also has approximately the same dimensions in the x-y plane as the semiconductor chip. The chip is mounted just above this core region. The second region is a peripheral region which surrounds the core region in the x-y plane. This second region has a CTE approximately equal to that of the printed circuit board CTE. During thermal cycling, the materials expand and contract. The core region expands at nearly the same rate as the chip and the area outside the chip footprint, the peripheral region, expands at a rate similar to that of the printed circuit board. This characteristic prevents thermal stress-induced fatigue on the package components and solder joints.
摘要翻译：具有在x-y平面上具有不同热膨胀系数（CTE）的集成芯片载体的集成电路芯片封装。芯片载体由两个主要区域组成。第一个是具有大约等于半导体芯片CTE的CTE的核心区域。该芯区域在半导体芯片的x-y平面上也具有大致相同的尺寸。芯片安装在该核心区域的正上方。第二区域是围绕x-y平面中的芯区域的周边区域。该第二区域的CTE大致等于印刷电路板CTE的CTE。在热循环过程中，物料膨胀和收缩。核心区域以与芯片和芯片占用面积以外的面积几乎相同的速率扩展，周边区域以与印刷电路板类似的速率扩展。该特性可防止封装部件和焊点发生热应力引起的疲劳。

2. 发明授权

US06214525B1 Printed circuit board with circuitized cavity and methods of producing same 失效
标题翻译：具有电路腔的印刷电路板及其制造方法
公开(公告)号：US06214525B1
公开(公告)日：2001-04-10
申请号：US09379774
申请日：1999-08-24
申请人： Christina Marie Boyko , Donald Seton Farquhar , Robert Maynard Japp , Michael Joseph Klodowski
发明人： Christina Marie Boyko , Donald Seton Farquhar , Robert Maynard Japp , Michael Joseph Klodowski
IPC分类号： G03F700
CPC分类号： H01L23/5385 , H01L21/486 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16235 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/15153 , H01L2924/1517 , H01L2924/3025 , H05K3/4697 , Y10S430/146
摘要： The invention relates to subtractive and additive processes for creating a circuitized cavity in a printed circuit board. Additionally, the invention includes a circuitized cavity and a printed circuit board with a circuitized cavity. The circuitized cavity provides for a variety of advantages over wire bonds.
摘要翻译：本发明涉及用于在印刷电路板中产生电路化空腔的减法和添加方法。另外，本发明包括电路化空腔和具有电路化空腔的印刷电路板。电路化空腔提供了超过引线键的各种优点。

3. 发明授权

US6066386A Printed circuit board with cavity for circuitization 失效
标题翻译：带空腔的印刷电路板进行电路化
公开(公告)号：US6066386A
公开(公告)日：2000-05-23
申请号：US57844
申请日：1998-04-09
申请人： Christina Marie Boyko , Donald Seton Farquhar , Robert Maynard Japp , Michael Joseph Klodowski
发明人： Christina Marie Boyko , Donald Seton Farquhar , Robert Maynard Japp , Michael Joseph Klodowski
IPC分类号： H01L21/48 , H01L23/538 , H05K3/46 , B32B3/00
CPC分类号： H05K3/4611 , H01L21/486 , H01L23/5385 , H01L2924/0002 , Y10S428/901 , Y10T29/49126 , Y10T29/49158 , Y10T29/49163 , Y10T29/49165 , Y10T428/24273 , Y10T428/24917
摘要： A method for making a printed circuit with a cavity is disclosed. The method comprises the step of laying a sticker sheet on a first, metallized dielectric layer and laying a second, metallized dielectric layer on the sticker sheet. The second metallized dielectric layer and the sticker sheet each have a window which is registered with the other window forming a cavity. Next, a flexible release layer is laid above the second metallized dielectric layer and a thermosetting visco-plastic material is laid on the release layer over the cavity. Next the first and second metallized dielectric layers, sticker sheet, release layer and visco-plastic material are laminated by heat and pressure to cure the sticker sheet and thereby bind the first and second metallized dielectric sheets to each other. During the lamination step, the sticker sheet flows to the perimeter of the cavity. However, the pressure forces the visco-plastic material tightly into the cavity to seal a bottom perimeter of the cavity such that the sticker sheet forms a smooth fillet at the bottom perimeter of the cavity.
摘要翻译：公开了一种用于制造具有空腔的印刷电路的方法。该方法包括以下步骤：将贴纸贴在第一金属化电介质层上，并在贴纸上铺设第二金属化电介质层。第二金属化介电层和贴纸各自具有与形成空腔的另一窗口对准的窗口。接下来，将柔性释放层铺设在第二金属化介电层上方，并且将热固性粘塑材料铺设在空腔上的释放层上。接下来，通过热和压力层压第一和第二金属化介电层，贴纸，剥离层和粘塑材料以固化粘合片，从而将第一和第二金属化介电片彼此粘合。在层压步骤期间，贴片片流动到空腔的周边。然而，压力迫使粘塑性材料紧密地进入空腔中以密封空腔的底部周边，使得粘贴片在空腔的底部周边处形成平滑的圆角。

4. 发明授权

US5784782A Method for fabricating printed circuit boards with cavities 失效
标题翻译：具有空腔的印刷电路板的制造方法
公开(公告)号：US5784782A
公开(公告)日：1998-07-28
申请号：US709373
申请日：1996-09-06
申请人： Christina Marie Boyko , Donald Seton Farquhar , Robert Maynard Japp , Michael Joseph Klodowski
发明人： Christina Marie Boyko , Donald Seton Farquhar , Robert Maynard Japp , Michael Joseph Klodowski
IPC分类号： H01L21/48 , H01L23/538 , H05K3/46 , H05K3/10 , H05K3/36 , H05K3/42
CPC分类号： H05K3/4611 , H01L21/486 , H01L23/5385 , H01L2924/0002 , Y10S428/901 , Y10T29/49126 , Y10T29/49158 , Y10T29/49163 , Y10T29/49165 , Y10T428/24273 , Y10T428/24917
摘要： A method for making a printed circuit with a cavity is disclosed. The method comprises the step of laying a sticker sheet on a first, metallized dielectric layer and laying a second, metallized dielectric layer on the sticker sheet. The second metallized dielectric layer and the sticker sheet each have a window which is registered with the other window forming a cavity. Next, a flexible release layer is laid above the second metallized dielectric layer and a thermosetting visco-plastic material is laid on the release layer over the cavity. Next, the first and second metallized dielectric layers, sticker sheet, release layer and visco-plastic material are laminated by heat and pressure to cure the sticker sheet and thereby bind the first and second metallized dielectric sheets to each other. During the lamination step, the sticker sheet flows to the perimeter of the cavity. However, the pressure forces the visco-plastic material tightly into the cavity to seal a bottom perimeter of the cavity such that the sticker sheet forms a smooth fillet at the bottom perimeter of the cavity.
摘要翻译：公开了一种用于制造具有空腔的印刷电路的方法。该方法包括以下步骤：将贴纸贴在第一金属化电介质层上，并在贴纸上铺设第二金属化电介质层。第二金属化介电层和贴纸各自具有与形成空腔的另一窗口对准的窗口。接下来，将柔性释放层铺设在第二金属化介电层上方，并且将热固性粘塑材料铺设在空腔上的释放层上。接下来，通过热和压力层叠第一和第二金属化电介质层，贴纸，剥离层和粘塑材料，以固化贴纸，从而将第一和第二金属化电介质片材彼此结合。在层压步骤期间，贴片片流动到空腔的周边。然而，压力迫使粘塑性材料紧密地进入空腔中以密封空腔的底部周边，使得粘贴片在空腔的底部周边处形成平滑的圆角。

5. 发明授权

US06534179B2 Halogen free triazines, bismaleimide/epoxy polymers, prepregs made therefrom for circuit boards and resin coated articles, and use 有权
标题翻译：无卤素三嗪，双马来酰亚胺/环氧聚合物，由其制成的用于电路板和树脂涂覆制品的预浸料，以及使用
公开(公告)号：US06534179B2
公开(公告)日：2003-03-18
申请号：US09818458
申请日：2001-03-27
申请人： Robert Maynard Japp , Konstantinos I. Papathomas , Mark D. Poliks
发明人： Robert Maynard Japp , Konstantinos I. Papathomas , Mark D. Poliks
IPC分类号： B32B2704
CPC分类号： B32B15/08 , B32B27/281 , B32B27/38 , B32B2457/08 , C08G59/304 , C08G59/3254 , C08L63/00 , C08L79/04 , C08L79/085 , H05K1/0373 , H05K2201/012 , Y10T428/2938 , Y10T428/31511 , Y10T428/31529 , C08L2666/20
摘要： A halogen-free dielectric resin mixture is described for use in microvia and other similar applications. The resin mixture contains a cyanate ester monomer or prepolymer a bismaleimide, an epoxy and a flame inhibiting compound selected from the group consisting of a phosphinic acid anhydride, a phosphonic acid andydride and a phosphonic acid half-ester. The flame inhibitor is present in an amount wherein the elemental phosphorus content is between about 2% and about 20% by weight, based on the weight of the resin mixture. The resin mixture can also include one or more coloring, fluorescent and UV absorbing agents. Prepregs based on the resin mixture with inorganic or organic reinforcing agents, as well as circuit boards and chip carriers made from the prepregs are also described. A resin coated article for use in microvia laser applications is likewise included.
摘要翻译：描述了一种无卤介电树脂混合物用于微孔和其它类似应用。树脂混合物含有氰酸酯单体或预聚物，双马来酰亚胺，环氧树脂和选自次膦酸酐，膦酸和二卤化物和膦酸半酯的阻燃化合物。阻燃剂的存在量，其中基于树脂混合物的重量，元素磷含量为约2重量％至约20重量％。树脂混合物还可以包括一种或多种着色剂，荧光剂和UV吸收剂。还描述了基于与无机或有机增强剂的树脂混合物的预浸料，以及由预浸料制成的电路板和芯片载体。同样包括用于微孔激光应用的树脂涂层制品。

6. 发明授权

US6136733A Method for reducing coefficient of thermal expansion in chip attach packages 失效
标题翻译：降低芯片连接封装热膨胀系数的方法
公开(公告)号：US6136733A
公开(公告)日：2000-10-24
申请号：US874902
申请日：1997-06-13
申请人： Lawrence Robert Blumberg , Robert Maynard Japp , William John Rudik , John Frank Surowka
发明人： Lawrence Robert Blumberg , Robert Maynard Japp , William John Rudik , John Frank Surowka
IPC分类号： B32B5/28 , H05K1/03 , B32B5/26 , C09J5/02
CPC分类号： B32B5/28 , H05K1/036 , H05K1/0366 , H05K2201/029 , H05K2201/0293 , H05K2201/068 , Y10T29/4913
摘要： A simple, inexpensive, drillable, reduced CTE laminate and circuitized structures comprising the reduced CTE laminate, is provided. The reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0.05% to 0.3%, preferably from about 0.08% to 0.10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The present invention also generally relates to a method for reducing the CTE of circuitized structures, and to methods for making reduced CTE laminate and circuitized structures comprising reduced CTE laminate. The method for making reduced CTE laminate and laminate structures comprises the following steps: providing non-woven quartz mat; providing a prepreg, preferably B-stage cured to not more than about 40%, preferably not more than 30% of full cure; sandwiching the non-woven quartz mat between two layers of prepreg, and reflowing the resin of the prepreg into the quartz mat. Optionally, the reduced CTE laminate is sandwiched between two layers of metal, preferably copper.
摘要翻译：提供了一种简单，便宜，可钻，减少的CTE层压板和包括减小的CTE层压板的电路结构。减少的CTE层压材料包括：约40％至75％，优选约55％至65％的树脂; 约0.05％至0.3％，优选约0.08％至0.10％的固化剂; 约25％至60％，优选约30％至40％的织布; 约1％至15％，优选约5％至10％体积的无纺石英垫。本发明还通常涉及一种用于减小电路化结构的CTE的方法，以及用于制造减少的CTE层压体和包括减少的CTE层压体的电路化结构的方法。制造减薄的CTE层压板和层压结构的方法包括以下步骤：提供无纺石英垫; 提供预浸料，优选B阶固化至不超过完全固化的约40％，优选不超过30％; 将无纺石英垫夹在两层预浸料之间，并将预浸料坯的树脂回流到石英垫中。任选地，还原的CTE层压体夹在两层金属之间，优选为铜。

7. 发明授权

US5858461A Technique for forming resin-impregnated fiberglass sheets with improved resistance to pinholing 失效
公开(公告)号：US5858461A
公开(公告)日：1999-01-12
申请号：US891629
申请日：1997-07-09
申请人： Bernd Karl Appelt , Robert Maynard Japp , Kostantinos Papathomas , William John Rudik
发明人： Bernd Karl Appelt , Robert Maynard Japp , Kostantinos Papathomas , William John Rudik
IPC分类号： B29B15/12 , B29C70/08 , B29C70/22 , B32B15/14 , C03C25/10 , C03C25/12 , C03C25/26 , C03C25/48 , C08J3/24 , C08J5/04 , D06N7/00 , H01L23/498 , H05K1/03 , H05K3/02 , B32B31/08 , B32B7/00
CPC分类号： H05K1/0366 , B29B15/125 , B29C70/086 , B29C70/088 , B29C70/22 , B32B15/14 , C03C25/10 , C03C25/12 , C03C25/26 , C03C25/48 , C08J3/243 , H01L23/49894 , B29C2791/001 , B29K2063/00 , B29K2105/0809 , B29K2105/24 , B29K2105/243 , B29K2705/00 , B29L2009/00 , C08J2363/00 , H01L2924/0002 , H05K2201/0154 , H05K2201/0166 , H05K2201/029 , H05K3/022 , Y10S428/901 , Y10T428/2857 , Y10T428/2929 , Y10T428/2931 , Y10T442/131 , Y10T442/2025 , Y10T442/2041 , Y10T442/2057 , Y10T442/2098
摘要： A method for coating cloth especially fiberglass sheets with a resin and resulting structure is provided. The coating is performed in two steps. In the first step, essentially all of the strands of the fiberglass are coated with the resin solvent mixture as well as most of the interstices or openings, although some of the interstices or openings have holes where the coating does not completely fill in. This first coating is then partially cured to the extent that it will not redissolve in a second coating of the same resin solution. The coated fiberglass with partially cured resin thereon is then given a second coating of the same resin mixture which coats the first coating and fills in any holes in the first coating. This second coating is then partially cured, which advances the cure of the first coating and results in an impregnated fiberglass cloth structure for use as sticker sheets. This substantially reduces pinholing.

8. 发明授权

US5756405A Technique for forming resin-impregnated fiberglass sheets 失效
公开(公告)号：US5756405A
公开(公告)日：1998-05-26
申请号：US716814
申请日：1996-09-10
申请人： Bernd Karl Appelt , William Thomas Fotorny , Robert Maynard Japp , Kostantinos Papathomas , Mark David Poliks
发明人： Bernd Karl Appelt , William Thomas Fotorny , Robert Maynard Japp , Kostantinos Papathomas , Mark David Poliks
IPC分类号： B29B15/12 , B29C70/22 , B29C70/54 , B32B15/04 , B32B27/04 , B32B27/38 , B32B37/00 , C03C25/10 , C03C25/12 , C03C25/26 , C03C25/50 , C08J3/24 , C08J5/04 , C08J5/24 , D06N7/00 , H01L23/498 , H05K1/03 , H05K3/02 , B32B31/08 , B32B7/00
CPC分类号： B32B37/0038 , B29B15/125 , B29C70/22 , B29C70/543 , B32B15/04 , B32B27/04 , B32B27/38 , C03C25/10 , C03C25/12 , C03C25/26 , C03C25/50 , C08J3/243 , C08J3/244 , C08J3/245 , C08J5/24 , H01L23/49894 , H05K1/0366 , B29K2063/00 , B29L2031/3425 , B32B2305/18 , B32B2311/12 , B32B2457/08 , C08J2363/00 , H01L2924/0002 , H05K2201/0154 , H05K2201/0166 , H05K2201/029 , H05K3/022 , Y10S428/901 , Y10T428/2857 , Y10T428/2929 , Y10T428/2931 , Y10T442/131 , Y10T442/2025 , Y10T442/2041 , Y10T442/2057 , Y10T442/2098 , Y10T442/2738
摘要： A method for coating cloth especially fiberglass sheets with a resin and resulting structure is provided. The coating is performed in two steps. In the first step, essentially all of the strands of the fiberglass are coated with the resin solvent mixture while maintaining the interstices or openings essentially free of the solvent mixture. This first coating is then partially cured to the extent that it will not redissolve in a second coating of the same resin solution. The coated fiberglass with partially cured resin thereon is then given a second coating of the same resin mixture which coats the first coating and fills in the interstices between the fibers. This second coating is then partially cured, which advances the cure of the first coating and results in an impregnated fiberglass cloth structure for use as sticker sheets. During lamination, the first coating acts like an impenetrable insulating sheet, preventing resin displacement and, therefore, preventing glass fiber contact with the conductive planes. The second coating is fluid enough to fill in spaces in the planes and to form the adhesive bond to cores and conductive layers.

9. 发明授权

US06387830B1 Method for reducing coefficient of thermal expansion in chip attach packages 失效
标题翻译：降低芯片连接封装热膨胀系数的方法
公开(公告)号：US06387830B1
公开(公告)日：2002-05-14
申请号：US09265210
申请日：1999-03-10
申请人： Lawrence Robert Blumberg , Robert Maynard Japp , William John Rudik , John Frank Surowka
发明人： Lawrence Robert Blumberg , Robert Maynard Japp , William John Rudik , John Frank Surowka
IPC分类号： B32B526
CPC分类号： B32B5/26 , B32B5/02 , B32B5/28 , B32B2260/023 , B32B2260/046 , B32B2262/101 , B32B2305/20 , B32B2553/00 , H05K1/036 , H05K1/0366 , H05K2201/029 , H05K2201/0293 , H05K2201/068 , Y10T29/4913 , Y10T442/2361 , Y10T442/2992 , Y10T442/3537 , Y10T442/3569 , Y10T442/3577 , Y10T442/3585 , Y10T442/3602 , Y10T442/3659
摘要： A simple, inexpensive, drillable, reduced CTE laminate and circuitized structures comprising the reduced CTE laminate, is provided. The reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0.05% to 0.3%, preferably from about 0.08% to 0.10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The present invention also generally relates to a method for reducing the CTE of circuitized structures, and to methods for making reduced CTE laminate and circuitized structures comprising reduced CTE laminate. The method for making reduced CTE laminate and laminate structures comprises the following steps: providing non-woven quartz mat; providing a prepreg, preferably not B-stage cured to not more than about 40%, preferably not more than 30% of full cure; sandwiching the non-woven quartz mat between two layers of prepreg, and reflowing the resin of the prepreg into the quartz mat. Optionally, the reduced CTE laminate is sandwiched between two layers of metal, preferably copper.
摘要翻译：提供了一种简单，便宜，可钻，减少的CTE层压板和包括减小的CTE层压板的电路结构。减少的CTE层压材料包括：约40％至75％，优选约55％至65％的树脂; 约0.05％至0.3％，优选约0.08％至0.10％的固化剂; 约25％至60％，优选约30％至40％的织布; 约1％至15％，优选约5％至10％体积的无纺石英垫。本发明还通常涉及一种用于减小电路化结构的CTE的方法，以及用于制造减少的CTE层压体和包括减少的CTE层压体的电路化结构的方法。制造减薄的CTE层压板和层压结构的方法包括以下步骤：提供无纺石英垫; 提供预浸料，优选不B阶固化至不超过完全固化的约40％，优选不超过30％; 将无纺石英垫夹在两层预浸料之间，并将预浸料坯的树脂回流到石英垫中。任选地，还原的CTE层压体夹在两层金属之间，优选为铜。

10. 发明授权

US06387205B1 Dustfree prepreg and method for making an article based thereon 失效
标题翻译：无尘预浸料及其制备方法
公开(公告)号：US06387205B1
公开(公告)日：2002-05-14
申请号：US09489724
申请日：2000-01-24
申请人： Bernd Karl Appelt , William Thomas Fotorny , Robert Maynard Japp , Kostantinos Papathomas , Mark David Poliks
发明人： Bernd Karl Appelt , William Thomas Fotorny , Robert Maynard Japp , Kostantinos Papathomas , Mark David Poliks
IPC分类号： B32B3126
CPC分类号： C08J3/243 , B29B15/125 , B29C70/08 , B29C70/086 , B29C70/088 , B29C70/22 , B29C70/543 , B29C2791/001 , B29K2063/00 , B29K2101/10 , B29K2105/0809 , B29K2105/24 , B29K2105/243 , B29K2105/256 , B29K2705/00 , B29L2009/00 , B29L2031/3425 , B32B15/14 , B32B27/04 , B32B27/38 , B32B37/0038 , B32B2305/18 , B32B2311/12 , B32B2457/08 , C03C25/10 , C03C25/12 , C03C25/26 , C03C25/48 , C03C25/50 , C08J3/244 , C08J3/245 , C08J5/04 , C08J5/24 , C08J2363/00 , D06N3/0022 , D06N2205/20 , H01L23/145 , H01L23/49894 , H01L2924/0002 , H05K1/0366 , H05K3/022 , H05K2201/0154 , H05K2201/0166 , H05K2201/029 , Y10S428/901 , Y10T428/2857 , Y10T428/2929 , Y10T428/2931 , Y10T442/131 , Y10T442/2025 , Y10T442/2041 , Y10T442/2049 , Y10T442/2057 , Y10T442/2098 , H01L2924/00
摘要： A method for coating cloth especially fiberglass sheets with a thermosetting resin and resulting structure is provided. The coating is performed in two steps. In the first step, essentially all of the strands of the fiberglass are coated with the resin/solvent mixture while maintaining at least some of the interstices or openings essentially free of the solvent mixture. This first coating is then partially cured to between about 70% and 90% of full cure. The coated fiberglass with partially cured resin thereon is then given a second coating of either the same or different thermosetting resin mixture which coats the first coating and fills in the interstices between the fibers. This second coating is then partially cured, which advances the cure of the first coating past 80% full cure and results in an impregnated fiberglass cloth structure for use as sticker sheets. During lamination, the first coating acts like an impenetrable insulating sheet, preventing resin displacement and, therefore, preventing glass fiber contact with the conductive planes. The second coating is fluid enough to fill in spaces in the planes and to form the adhesive bond to cores and conductive layers. The structure reduces the tendency of the resin to flake and produce dust during subsequent processing operations.
摘要翻译：提供了一种用热固性树脂涂布布尤其是玻璃纤维片并得到结构的方法。涂层分两步进行。在第一步骤中，玻璃纤维的基本上所有的股线都涂覆有树脂/溶剂混合物，同时保持至少一些间隙或开口基本上不含溶剂混合物。然后将该第一涂层部分固化至完全固化的约70％至90％之间。然后将其上具有部分固化的树脂的涂覆的玻璃纤维给予相同或不同的热固性树脂混合物的第二涂层，所述热固性树脂混合物涂覆第一涂层并填充纤维之间的间隙。然后将该第二涂层部分固化，这使得第一涂层的固化达到80％全固化，并且导致浸渍的玻璃纤维布结构用作贴纸。在层压期间，第一涂层的作用类似于不可渗透的绝缘片，防止树脂移位，因此防止玻璃纤维与导电平面接触。第二涂层是足够流体以填充平面中的空间并形成与芯和导电层的粘合剂粘合剂。该结构降低了在随后的加工操作期间树脂剥落并产生灰尘的倾向。

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