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1. 发明授权

US06579758B2 Method and installation for fabricating one-sided buried straps 有权
标题翻译：制造单面埋地带的方法和安装
公开(公告)号：US06579758B2
公开(公告)日：2003-06-17
申请号：US10186656
申请日：2002-07-01
申请人： Bernd Göbel , Martin Gutsche , Alfred Kersch , Werner Steinhögl
发明人： Bernd Göbel , Martin Gutsche , Alfred Kersch , Werner Steinhögl
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L21/32139
摘要： Buried straps are produced on one side in deep trench structures. A PVD process is used to deposit masking material in the recess inclined at an angle. As a result, a masking wedge is produced on the buried strap, on one side in the base region of the recess. The masking wedge serves as a mask during a subsequent anisotropic etching step, which is carried out selectively with respect to the masking wedge, for removing the buried strap on one side.
摘要翻译：在深沟槽结构中的一侧产生埋管带。 PVD工艺用于在一定角度倾斜的凹槽中沉积掩模材料。结果，在凹陷的基部区域的一侧上的掩埋带上产生掩蔽楔。在随后的各向异性蚀刻步骤期间，掩模楔用作掩模，其相对于掩模楔选择性地执行，用于在一侧上移除掩埋带。

2. 发明授权

US06977405B2 Semiconductor memory with memory cells comprising a vertical selection transistor and method for fabricating it 失效
标题翻译：具有包括垂直选择晶体管的存储单元的半导体存储器及其制造方法
公开(公告)号：US06977405B2
公开(公告)日：2005-12-20
申请号：US10792742
申请日：2004-03-05
申请人： Jörn Lützen , Bernd Goebel , Dirk Schumann , Martin Gutsche , Harald Seidl , Martin Popp , Alfred Kersch , Werner Steinhögl
发明人： Jörn Lützen , Bernd Goebel , Dirk Schumann , Martin Gutsche , Harald Seidl , Martin Popp , Alfred Kersch , Werner Steinhögl
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10867 , H01L27/10891
摘要： In order to fabricate a semiconductor memory, a trench capacitor is arranged in a first trench. Beside the first trench, a first longitudinal trench and, parallel on the other side of the first trench, a second longitudinal trench are arranged in the substrate. A first spacer word line is arranged in the first longitudinal trench and a second spacer word line is arranged in the second longitudinal trench. There are arranged in the first trench connecting webs between the first spacer word line and the second spacer word line which have a thickness which, in the direction of the first spacer word line, is less than half the width of the first trench in the direction of the first spacer word line.
摘要翻译：为了制造半导体存储器，在第一沟槽中布置有沟槽电容器。在第一沟槽的旁边，在衬底中布置有第一纵向沟槽，并且在第一沟槽的另一侧平行的第二纵向沟槽。第一间隔字线布置在第一纵向沟槽中，第二间隔字线布置在第二纵向沟槽中。布置在第一沟槽中，连接腹板之间的第一隔离物字线和第二隔离物字线之间的厚度，该厚度在第一隔离物字线的方向上小于第一沟槽的方向上的宽度的一半的第一个间隔字线。

3. 发明授权

US07413971B2 Method of producing a layered arrangement and layered arrangement 失效
标题翻译：制造层叠布置和分层布置的方法
公开(公告)号：US07413971B2
公开(公告)日：2008-08-19
申请号：US10498421
申请日：2002-10-23
申请人： Werner Steinhögl , Franz Kreupl , Wolfgang Hönlein
发明人： Werner Steinhögl , Franz Kreupl , Wolfgang Hönlein
IPC分类号： H01L21/44
CPC分类号： H01L21/7682 , B82Y10/00 , H01L51/0048 , H01L2221/1047 , Y10S977/742
摘要： An arrangement and process for producing a circuit arrangement is disclosed. The process includes having a layer arrangement, in which two electrically conductive interconnects running substantially parallel to one another are formed on a substrate. At least one auxiliary structure is formed on the substrate and between the two interconnects, running in a first direction, which first direction includes an angle of between 45 degrees and 90 degrees with a connecting axis of the interconnects, running orthogonally with respect to the two interconnects, the at least one auxiliary structure being produced from a material which allows the at least one auxiliary structure to be selectively removed from a dielectric layer. The dielectric layer is formed between the two interconnects, in such a manner that the at least one auxiliary structure is at least partially covered by the dielectric layer.
摘要翻译：公开了一种用于制造电路装置的装置和方法。该方法包括具有层布置，其中在基板上形成基本上彼此平行延伸的两个导电互连。至少一个辅助结构形成在基板上并且在两个互连之间并且在第一方向上延伸，该第一方向与互连件的连接轴线成45度到90度之间的角度，相对于两个互连件正交地运行所述至少一个辅助结构由允许所述至少一个辅助结构从电介质层选择性地去除的材料制成。介电层形成在两个互连之间，使得至少一个辅助结构至少部分地被电介质层覆盖。

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