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1. 发明授权

US4868624A Channel collector transistor 失效
标题翻译：通道集电极晶体管
公开(公告)号：US4868624A
公开(公告)日：1989-09-19
申请号：US841012
申请日：1986-03-14
申请人： Bernard L. Grung , Raymond M. Warner, Jr. , Thomas E. Zipperian
发明人： Bernard L. Grung , Raymond M. Warner, Jr. , Thomas E. Zipperian
IPC分类号： H01L29/06 , H01L29/08 , H01L29/36 , H01L29/73 , H01L29/84
CPC分类号： H01L29/36 , H01L29/0692 , H01L29/0821 , H01L29/7302 , H01L29/7317 , H01L29/84
摘要： A monolithic semiconductor transistor structure is described wherein the active collector region of a bipolar-junction transistor is physically and operatively merged with the channel region of a junction field-effect transistor, providing a composite circuit which approximates a cascode configuration. By controlling the integral of the net impurity doping concentration to various active regions of the device, the active collector region of a bipolar-junction transistor configuration is made sufficiently thin so as to simultaneously function as an active collector region as well as a channel region of one or more field-effect transistors. The channel-collector transistor provides high breakdown voltage, high dynamic resistance and linearity over a wide voltage range, and is compatible with solid-state batch fabrication processes for direct incorporation into larger integrated circuits. The device is particularly suitable for linear applications. Improved operating current is obtained and current limiting constraints of the device are minimized by cooperative emitter and base configurations, topologically extended to maximize use of available circuit area. Interdigitated base and collector region layout further improves operating performance.
摘要翻译：描述了单片半导体晶体管结构，其中双极结晶体管的有源集电极区域物理地和可操作地与结型场效应晶体管的沟道区域合并，提供近似共源共栅配置的复合电路。通过控制器件的各种有源区域的净杂质掺杂浓度的积分，双极结晶体管结构的有源集电极区域被制成足够薄，以同时用作有源集电极区域以及沟道区域一个或多个场效应晶体管。通道集电极晶体管在宽电压范围内提供高击穿电压，高动态电阻和线性度，并且与固态批量制造工艺兼容，可直接并入大型集成电路。该器件特别适用于线性应用。获得了改进的工作电流，并通过协同发射器和基极配置来最小化器件的限流约束，拓扑拓展到最大限度地利用可用电路面积。交叉的基极和集电极区域布局进一步提高了操作性能。

2. 发明授权

US4794442A Three-dimensional integrated circuit 失效
标题翻译：三维集成电路
公开(公告)号：US4794442A
公开(公告)日：1988-12-27
申请号：US799652
申请日：1985-11-19
申请人： Raymond M. Warner, Jr. , Ronald D. Schrimpf , Alfons Tuszynski
发明人： Raymond M. Warner, Jr. , Ronald D. Schrimpf , Alfons Tuszynski
IPC分类号： H01L21/74 , H01L21/76 , H01L21/761 , H01L21/822 , H01L27/06 , H01L29/808 , H01L27/02 , H01L29/80 , H01L29/88
CPC分类号： H01L21/8221 , H01L21/74 , H01L21/76 , H01L21/761 , H01L27/0688 , H01L29/808
摘要： A single-crystal monolith containing a 3-D doping pattern forming varied devices and circuits that are junction-isolated. The semiconductor monolith includes interconnecting signal paths and power buses, also junction-isolated, usually with N+ regions within P matrix regions, and tunnel junctions, N+-P+ junctions, as ohmic contacts from N-type to P-type regions. An isolating box incorporates an orthogonal isolator. The 3-D structure places layers of critical profile normal to the growth axis. The orthogonal isolator can include floating elements. The 3-D semiconductor monolith can be manufactured through continuous or quasicontinuous processing in a closed system, such as through MBE or sputter epitaxy.
摘要翻译：包含3-D掺杂图案的单晶整体形成不同的器件和被隔离的电路。半导体整体件包括互连信号路径和电源总线，其也是结隔离的，通常具有P个矩阵区域内的N +区域，以及隧道结，N + -P +结，作为从N型到P型区域的欧姆接触。隔离箱包括正交隔离器。 3-D结构使关键轮廓的层与生长轴垂直。正交隔离器可以包括浮动元件。可以通过在封闭系统中的连续或准连续处理（例如通过MBE或溅射外延）来制造3-D半导体整体。

3. 发明授权

US06344116B2 Monocrystalline three-dimensional integrated-circuit technology 失效
标题翻译：单晶三维集成电路技术
公开(公告)号：US06344116B2
公开(公告)日：2002-02-05
申请号：US09198220
申请日：1998-11-23
申请人： Raymond M. Warner, Jr. , John E. MacCrisken
发明人： Raymond M. Warner, Jr. , John E. MacCrisken
IPC分类号： C23C1434
CPC分类号： H01L21/761 , H01L21/74 , H01L21/76 , H01L21/8221 , H01L27/0688 , H01L29/808
摘要： Three technologies realize monocrystalline three-dimensional (3-D) integrated circuits: (1) silicon sputter epitaxy permitting fast growth at low temperature; (2) real-time pattern generation using a pixel-by-pixel programmable device to create a patterned beam of energetic radiation; and (3) flash diffusion focuses through a projector barrel the patterned beam on a silicon sample, causing localized dopant diffusion from a heavily doped region at the surface into the underlying region. Removing the heavily doped layer leaves a 2-D doping pattern. Creating additional 2-D patterns on top of it through process repetition produces a buried 3-D doping pattern. One configuration places projector barrel and sample in fixed positions inside the sputtering chamber and a ring of targets around the barrel facing the sample with targets of a given kind symmetrically positioned in the ring. Cobalt can be substituted for the doping layer and can be driven in creating silicide conductive patterns.
摘要翻译：三种技术实现单晶三维（3-D）集成电路：（1）硅溅射外延允许在低温下快速生长; （2）使用逐像素可编程设备的实时图案生成，以创建图案化的能量辐射束; 和（3）闪光扩散通过投影仪将图案化的光束对准在硅样品上，引起局部掺杂剂从表面的重掺杂区域扩散到下面的区域。去除重掺杂层留下2-D掺杂图案。通过过程重复创建其上的2-D图案，产生埋入的3-D掺杂图案。一个配置将投影机镜筒和样品放置在溅射室内的固定位置，并且围绕筒的面向样品的靶环对称地定位在环中。钴可以代替掺杂层，并且可以在产生硅化物导电图案中被驱动。

4. 发明授权

US5089862A Monocrystalline three-dimensional integrated circuit 失效
标题翻译：单晶三维集成电路
公开(公告)号：US5089862A
公开(公告)日：1992-02-18
申请号：US443175
申请日：1989-11-30
申请人： Raymond M. Warner, Jr. , Ronald D. Schrimpf , Alfons Tuszynski
发明人： Raymond M. Warner, Jr. , Ronald D. Schrimpf , Alfons Tuszynski
IPC分类号： H01L21/203 , H01L21/74 , H01L21/76 , H01L21/761 , H01L21/822 , H01L27/06 , H01L29/808
CPC分类号： H01L21/8221 , H01L21/74 , H01L21/76 , H01L21/761 , H01L27/0688 , H01L29/808
摘要： A monocrystalline monolith contains a 3-D array of interconnected lattice-matched devices (which may be of one kind exclusively, or that kind in combination with one or more other kinds) performing digital, analog, image-processing, or neural-network functions, singly or in combination. Localized inclusions of lattice-matched metal and (or) insulator can exist in the monolith, but monolith-wide layers of insulator are avoided. The devices may be self-isolated, junction-isolated, or insulator-isolated, and may include but not be limited to MOSFETs, BJTs, JFETs, MFETs, CCDs, resistors, and capacitors. The monolith is fabricated in a single apparatus using a process such as MBE or sputter epitaxy executed in a continuous or quasicontinuous manner under automatic control, and supplanting hundreds of discrete steps with handling and storage steps interpolated. "Writing" on the growing crystal is done during crystal growth by methods that may include but not be limited to ion beams, laser beams, patterned light exposures, and physical masks. The interior volume of the fabrication apparatus is far cleaner and more highly controlled than that of a clean room. The apparatus is highly replicated and is amenable to mass production. The product has unprecedented volumetric function density, and high performance stems from short signal paths, low parasitic loading, and 3-D architecture. High reliability stems from contamination-free fabrication, small signal-arrival skew, and generous noise margins. Economy stems from mass-produced factory apparatus, automatic IC manufacture, and high IC yield. Among the IC products are fast and efficient memories with equally fast and efficient error-correction abilities, crosstalk-free operational amplifiers, and highly paralleled and copiously interconnected neural networks.
摘要翻译：单晶整体包含执行数字，模拟，图像处理或神经网络功能的互连网格匹配设备（其可以是一种专门地或者与一种或多种其他类型组合的那种）的3-D阵列，单独或组合使用。晶格匹配的金属和（或）绝缘体的局部夹杂物可以存在于整料中，但是避免了整体式的绝缘体层。器件可以是自隔离，结隔离或绝缘体隔离的，并且可以包括但不限于MOSFET，BJT，JFET，MFET，CCD，电阻器和电容器。使用诸如MBE或溅射外延的工艺在单个设备中制造整料，其在自动控制下以连续或准连续的方式执行，并且通过内插处理和存储步骤取代数百个离散步骤。通过可能包括但不限于离子束，激光束，图案化曝光和物理掩模的方法，在晶体生长期间，对晶体生长进行“写入”。制造装置的内部容积比洁净室的内部空间更清洁和更高度地控制。该设备高度复制，适合批量生产。该产品具有前所未有的体积功能密度，高性能源于短信号路径，低寄生负载和3-D架构。高可靠性来源于无污染的制造，信号到达偏差小，噪声容量大。经济源于批量生产的工厂设备，自动化IC制造，IC产量高。在IC产品中，快速有效的存储器具有同等快速和高效的纠错能力，无串扰运算放大器，以及高度平行和大量互连的神经网络。

5. 发明授权

US4190852A Photovoltaic semiconductor device and method of making same 失效
标题翻译：光伏半导体器件及其制造方法
公开(公告)号：US4190852A
公开(公告)日：1980-02-26
申请号：US942152
申请日：1978-09-14
申请人： Raymond M. Warner, Jr.
发明人： Raymond M. Warner, Jr.
IPC分类号： H01L27/142 , H01L27/14
CPC分类号： H01L31/047 , Y02E10/50
摘要： A photovoltaic semiconductor device which is a horizontal multijunction series-array solar battery with a monocrystalline body and having elongate zones of aluminum doped silicon passed entirely through N-type silicon layers by Thermomigration process to connect together epitaxially grown buried P layers. Masked elongate N diffusion zones which are parallel and substantially contiguous to each elongated P zone penetrates at least through the lowest P layer thereby forming an inactive pn junction. A thin shallow layer of P-type material is diffused across the top N-type layer. Topologically continuous photovoltaic junctions exist in each cell of the photovoltaic semiconductor device between the shallow layer of P-type material, the buried layer or layers of P-type material, the elongate zone of aluminum doped silicon, and the N-type silicon thereby forming active pn junctions. Metallic strips, at the other pn junctions formed by the thermomigrated aluminum which are inactive, electrically connect the cells together. A method is disclosed for manufacturing the photovoltaic semiconductor device.
摘要翻译：作为具有单晶体并且具有铝掺杂硅的细长区域的水平多结串联阵列太阳能电池的光电半导体器件通过热迁移工艺完全通过N型硅层，将外延生长的掩埋P层连接在一起。平行且基本上与每个细长P区连续的掩蔽的细长N扩散区至少穿过最低P层从而形成无活性pn结。 P型材料的薄浅层在顶层N型层上扩散。在P型材料的浅层，P型材料的掩埋层或者铝掺杂硅的细长区域和N型硅之间，在光电半导体器件的每个单元中存在拓扑连续的光伏结，从而形成活性pn结。在由热失活铝形成的其他pn结处的金属条电极将电池连接在一起。公开了一种用于制造光伏半导体器件的方法。

6. 发明授权

US5937318A Monocrystalline three-dimensional integrated circuit 失效
标题翻译：单晶三维集成电路
公开(公告)号：US5937318A
公开(公告)日：1999-08-10
申请号：US705726
申请日：1991-05-24
申请人： Raymond M. Warner, Jr. , Ronald D. Schrimpf , Alfons Tuszynski
发明人： Raymond M. Warner, Jr. , Ronald D. Schrimpf , Alfons Tuszynski
IPC分类号： H01L21/203 , H01L21/74 , H01L21/76 , H01L21/761 , H01L21/822 , H01L27/06 , H01L29/808 , H01L21/00
CPC分类号： H01L21/8221 , H01L21/74 , H01L21/76 , H01L21/761 , H01L27/0688 , H01L29/808
摘要： A monocrystalline monolith contains a 3-D array of interconnected lattice-matched devices (which may be of one kind exclusively, or that kind in combination with one or more other kinds) performing digital, analog, image-processing, or neural-network functions, singly or in combination. Localized inclusions of lattice-matched metal and (or) insulator can exist in the monolith, but monolith-wide layers of insulator are avoided. The devices may be self-isolated, junction-isolated, or insulator-isolated, and may include but not be limited to MOSFETs, BJTs, JFETs, MFETs, CCDs, resistors, and capacitors. The monolith is fabricated in a single apparatus using a process such as MBE or sputter epitaxy executed in a continuous or quasicontinuous manner under automatic control, and supplanting hundreds of discrete steps with handling and storage steps interpolated. "Writing" on the growing crystal is done during crystal growth by methods that may include but not be limited to ion beams, laser beams, patterned light exposures, and physical masks. The interior volume of the fabrication apparatus is far cleaner and more highly controlled than that of a clean room. The apparatus is highly, replicated and is amenable to mass production. The product has unprecedented volumetric function density, and high performance stems from short signal paths, low parasitic loading, and 3-D architecture. High reliability stems from contamination-free fabrication, small signal-arrival skew, and generous noise margins. Economy stems from mass-produced factory apparatus, automatic IC manufacture, and high IC yield. Among the IC products are fast and efficient memories with equally fast and efficient error-correction abilities, crosstalk-free operational amplifiers, and highly paralleled and copiously interconnected neural networks.
摘要翻译：单晶整体包含执行数字，模拟，图像处理或神经网络功能的互连网格匹配设备（其可以是一种专门地或者与一种或多种其他类型组合的那种）的3-D阵列，单独或组合使用。晶格匹配的金属和（或）绝缘体的局部夹杂物可以存在于整料中，但是避免了整体式的绝缘体层。器件可以是自隔离，结隔离或绝缘体隔离的，并且可以包括但不限于MOSFET，BJT，JFET，MFET，CCD，电阻器和电容器。使用诸如MBE或溅射外延的工艺在单个设备中制造整料，其在自动控制下以连续或准连续的方式执行，并且通过内插处理和存储步骤取代数百个离散步骤。通过可能包括但不限于离子束，激光束，图案化曝光和物理掩模的方法，在晶体生长期间，对晶体生长进行“写入”。制造装置的内部容积比洁净室的内部空间更清洁和更高度地控制。该设备高度复制，适合批量生产。该产品具有前所未有的体积功能密度，高性能源于短信号路径，低寄生负载和3-D架构。高可靠性来源于无污染的制造，信号到达偏差小，噪声容量大。经济源于批量生产的工厂设备，自动化IC制造，IC产量高。在IC产品中，快速高效的存储器具有同等快速和高效的纠错能力，无串扰运算放大器，以及高度平行且大量互连的神经网络。

7. 发明授权

US5840589A Method for fabricating monolithic and monocrystalline all-semiconductor three-dimensional integrated circuits 失效
标题翻译：单片和单晶全半导体三维集成电路的制造方法
公开(公告)号：US5840589A
公开(公告)日：1998-11-24
申请号：US468968
申请日：1995-06-06
申请人： Raymond M. Warner, Jr. , Ronald D. Schrimpf
发明人： Raymond M. Warner, Jr. , Ronald D. Schrimpf
IPC分类号： H01L21/203 , H01L21/74 , H01L21/76
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02631 , H01L21/74 , H01L21/76 , Y10S148/158
摘要： A method is described for growing a single crystal having three-dimensional (3-D) doping patterns created within it during growth while maintaining a plane growth surface, creating junction-isolated devices and interconnections, forming a 3-D integrated circuit (IC). The crystal is grown as a large number of lightly-doped layers in a single-pumpdown procedure using sputter epitaxy, which offers growth rates for good-quality silicon of at least 0.1 micrometer per minute. The process experiences a stable environment with temperature remaining around 400 C and pressure near 1 millitorr, and the process is "quasicontinuous" in that once each layer is in place, its surface will experience a short series of further steps that create a 2-D doping pattern extending through the layer. It is the merging of many such successive 2-D patterns that creates the desired 3-D doping pattern within the finished silicon crystal. Primary layer growth is the first step in a five-step process; second is the growth of a thinner secondary layer of heavily doped silicon to serve as a source of dopant; third is exposing the silicon surface to an intense, patterned, focused light flash from an LCD (or silicon mirror) pattern generator, causing localized dopant diffusion through the primary layer; fourth is the uniform removal by ion milling of a layer thicker than the secondary layer, thus eliminating all dopant from the primary layer except in the selected portions of it affected by the light-induced impurity diffusion; and fifth is a uniform flash annealing of the primary layer.
摘要翻译：描述了一种用于在生长期间生长具有在其内产生的三维（3-D）掺杂图案的单晶的方法，同时保持平面生长表面，产生结隔离器件和互连，形成3-D集成电路（IC）。在使用溅射外延的单次抽运程序中，晶体作为大量轻掺杂层生长，其提供至少0.1微米/分钟的优质硅的生长速率。该过程经历一个稳定的环境，温度保持在400℃左右，压力接近1毫托，并且该过程是“准连续”的，因为一旦每层都到位，其表面将经历一系列进一步的步骤，形成2-D 掺杂图案延伸穿过该层。许多这样连续的2-D图案的合并是在成品硅晶体内产生所需的3-D掺杂图案。初级层次增长是五步骤的第一步。第二个是重掺杂硅的较薄二次层的生长，用作掺杂剂源; 第三是将硅表面暴露于来自LCD（或硅镜）图案发生器的强烈的，图案化的聚焦光闪光，导致局部掺杂剂扩散通过主层; 第四是通过离子研磨均匀去除比二级层厚的层，从而除了受光诱导的杂质扩散影响的选定部分之外，从初级层除去所有的掺杂剂; 第五是初级层的均匀闪光退火。

8. 发明授权

US5111074A Multi-input compound function complementary noise-immune logic 失效
标题翻译：多输入复合功能补充无噪声逻辑
公开(公告)号：US5111074A
公开(公告)日：1992-05-05
申请号：US559162
申请日：1990-07-26
申请人： Roger J. Gravrok , Raymond M. Warner, Jr.
发明人： Roger J. Gravrok , Raymond M. Warner, Jr.
IPC分类号： H03K19/003 , H03K19/086
CPC分类号： H03K19/086 , H03K19/00353
摘要： A digital logic circuit having multiple inputs and a product-of-sums output uses multi input OR circuits with interacting constant-current and constant-voltage elements to improve voltage transfer characteristics. A second-level arbitration circuit connects to the OR circuits and provides mutually exclusive pull-up and pull-down control signals as a logical function of the states of the OR circuits. An output stage connects to the arbitration circuit. The output stage comprises pull-up and pull-down drivers responsive to the output of the second-level arbitration circuit. The digital logic circuit operates at high speed because its transistors are prevented from entering saturation. The logic circuit is easily expandable and provides a simple and direct method of implementing logic circuits which provide product-of-sums outputs.
摘要翻译：具有多个输入和总和输出的数字逻辑电路使用具有相互作用的恒定电流和恒定电压元件的多输入OR电路来改善电压传递特性。二级仲裁电路连接到OR电路，并提供互斥上拉和下拉控制信号作为OR电路状态的逻辑功能。输出级连接到仲裁电路。输出级包括响应于二级仲裁电路的输出的上拉和下拉驱动器。数字逻辑电路以高速运行，因为其晶体管被阻止进入饱和。逻辑电路易于扩展，并提供了实现提供产品总和输出的逻辑电路的简单而直接的方法。

9. 发明授权

US4885615A Monocrystalline three-dimensional integrated circuit 失效
标题翻译：单晶三维集成电路
公开(公告)号：US4885615A
公开(公告)日：1989-12-05
申请号：US861708
申请日：1986-05-12
申请人： Raymond M. Warner, Jr. , Ronald D. Schrimpf , Alfons Tuszynski
发明人： Raymond M. Warner, Jr. , Ronald D. Schrimpf , Alfons Tuszynski
IPC分类号： H01L21/74 , H01L21/76 , H01L21/761 , H01L21/822 , H01L27/06 , H01L29/808
CPC分类号： H01L21/8221 , H01L21/74 , H01L21/76 , H01L21/761 , H01L27/0688 , H01L29/808
摘要： A single-crystal monolith containing a 3-D doping pattern forming varied devices and circuits that are junction-isolated. The semiconductor monolith includes interconnecting signal paths and power buses, also junction-isolated, usually with N+ regions within P matrix regions, and tunnel junctions, N+ - P+ junctions, as ohmic contacts from N-type to P-type regions. An isolating box incorporates an orthogonal isolator. The 3-D structure places layers of critical profile normal to the growth axis. The orthogonal isolator can include floating elements. The 3-D semiconductor monolith can be manufactured through continuous or quasicontinuous processing in a closed system, such as through MBE or sputter epitaxy. Also, a thin layer of silicide can be provided as an ohmic contact and/or a thick layer of silicide can be provided as a conductor thereby providing monocrystalline 3-D devices or integrated circuits. Finally, an insulator can be provided about an entire device for isolation.
摘要翻译：包含3-D掺杂图案的单晶整体形成不同的器件和被隔离的电路。半导体整体包括互连信号路径和电源总线，也是结隔离的，通常具有P个矩阵区域内的N +区域，以及隧道结，N + -P +结，作为从N型到P型区域的欧姆接触。隔离箱包括正交隔离器。 3-D结构使关键轮廓的层与生长轴垂直。正交隔离器可以包括浮动元件。可以通过在封闭系统中的连续或准连续处理（例如通过MBE或溅射外延）来制造3-D半导体整体。此外，可以提供薄层的硅化物作为欧姆接触，和/或可以提供厚的硅化物层作为导体，从而提供单晶3-D器件或集成电路。最后，可以围绕整个设备提供绝缘体以进行隔离。

10. 发明授权

US4499515A Integrated magnetostrictive-piezoresistive magnetic recording playback head 失效
标题翻译：集成磁致伸缩压阻磁记录播放头
公开(公告)号：US4499515A
公开(公告)日：1985-02-12
申请号：US398419
申请日：1982-07-14
申请人： Chester Piotrowski , Neil W. Loeding , Raymond M. Warner, Jr.
发明人： Chester Piotrowski , Neil W. Loeding , Raymond M. Warner, Jr.
IPC分类号： G01R33/06 , G11B5/127 , G11B5/33 , G11B5/58 , H01L41/12 , G11B5/12 , G11B5/30
CPC分类号： G01R33/06 , G11B5/1278 , G11B5/332 , G11B5/58 , H01L41/125
摘要： A thin film magnetic recording playback head is disclosed wherein mechanically coupled films of a magnetostrictive material and of a piezoresistive material are utilized with a solid state amplifier electrically coupled to sense resistance changes in the piezoresistive film. In operation, localized magnetic patterns on a recording medium induce strain in the magnetostrictive film, which in turn induces in the piezoresistive film corresponding changes in electrical resistance.
摘要翻译：公开了一种薄膜磁记录重放头，其中磁致伸缩材料和压阻材料的机械耦合薄膜与电耦合以感测压阻薄膜中的电阻变化的固态放大器一起使用。在操作中，记录介质上的局部磁性图案在磁致伸缩膜中引起应变，这又导致压敏膜中相应的电阻变化。

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