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1. 发明授权

US5553301A Programmable sequencher having internal components which are microprocessor read/write interfacable 失效
标题翻译：具有内部组件的可编程顺控程序，它们是微处理器读/写可互操作的
公开(公告)号：US5553301A
公开(公告)日：1996-09-03
申请号：US24819
申请日：1993-03-01
申请人： Bernard J. New , Philip Freidin
发明人： Bernard J. New , Philip Freidin
IPC分类号： G06F9/26 , G06F9/22 , G06F11/36 , G06F13/20
CPC分类号： G06F9/22 , G06F11/3648
摘要： A single-chip microprogrammable sequencer (10) provides a bus (12) for connection of an external microprocessor. The sequencer includes a register file (40) which consists of a number of registers accessible to the microprocessor by which the microprocessor can monitor and control operation of the sequencer. The sequencer also includes a writeable control store (52) which is accessible to the microprocessor. Microinstructions may be written to the store by the microprocessor so that selected programs or program segments will be executed by the sequencer. A breakpoint register (104), included in the register file, is used in conjunction with a program counter portion of the sequencer providing a breakpoint facility for the microprocessor. Similarly, start, halt, reset and single-step operations may be performed by the sequencer under control of the microprocessor.
摘要翻译：单片微程序定序器（10）提供用于连接外部微处理器的总线（12）。定序器包括寄存器文件（40），寄存器文件（40）由微处理器可访问的多个寄存器组成，微处理器可以通过该寄存器文件监视和控制定序器的操作。定序器还包括可由微处理器访问的可写控制存储器（52）。微指令可以由微处理器写入存储器，以便选定的程序或程序段将由定序器执行。包括在寄存器文件中的断点寄存器（104）与定序器的程序计数器部分结合使用，为微处理器提供断点设备。类似地，在微处理器的控制下，定序器可以执行启动，停止，复位和单步操作。

2. 发明授权

US4933837A Methods and apparatus for optimizing instruction processing in computer systems employing a combination of instruction cache and high speed consecutive transfer memories 失效
标题翻译：使用指令高速缓存和高速连续传输存储器的组合来优化计算机系统中的指令处理的方法和装置
公开(公告)号：US4933837A
公开(公告)日：1990-06-12
申请号：US936193
申请日：1986-12-01
申请人： Philip Freidin
发明人： Philip Freidin
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F9/3808
摘要： Methods and apparatus are set forth for optimizing the performance of instruction processors using an instruction cache memory in combination with a sequential transfer main memory. According to the invention, the memory system stores preselected instructions in cache memory. The instructions are those that immediately follow a branch operation. The purpose of storing these instructions is to minimize, and if possible, eliminate the delay associated with fetching the same sequence from main memory following a subsequent branch to the same instruction string. The number of instructions that need to be cached (placed in cache memory) is a function of the access time for the first and subsequent fetches from sequential main memory, the speed of the cache memory, and instruction execution time. The invention is particularly well suited for use in computer systems having RISC architectures with fixed instruction lengths.
摘要翻译：阐述了使用与顺序传送主存储器组合的指令高速缓存存储器来优化指令处理器的性能的方法和装置。根据本发明，存储器系统将预先选择的指令存储在高速缓冲存储器中。这些说明是立即执行分支操作的指令。存储这些指令的目的是尽可能减少与后续分支到相同指令串之间从主存储器读取相同序列相关的延迟。需要缓存的指令数量（放置在高速缓冲存储器中）是从连续主存储器中获取的第一次和随后的访问时间，高速缓冲存储器的速度和指令执行时间的函数。本发明特别适用于具有固定指令长度的RISC架构的计算机系统。

3. 发明授权

US4935929A Diagnostic circiut for digital systems 失效
标题翻译：数字系统诊断电路
公开(公告)号：US4935929A
公开(公告)日：1990-06-19
申请号：US181626
申请日：1988-04-14
申请人： Steven B. Sidman , Philip Freidin
发明人： Steven B. Sidman , Philip Freidin
IPC分类号： G01R31/3185
CPC分类号： G01R31/318536 , G01R31/318572
摘要： In a circuit for selectively communicating data into and out of a signal path, typically used for diagnosing a data processing unit, a shadow register is used for receiving data from and transferring data to an external source. The shadow register is physically insulated from the signal path by a first state register and a second state register, the first state register transferring data from the signal path to the shadow register, the second state register transferring data between the shadow register and the signal path. Path switching is achieved by a selector connected to the respective outputs of the first and second state registers and responsive to a control signal for releasing output signals from only one of these registers.
摘要翻译：在用于选择性地将数据传送到通常用于诊断数据处理单元的信号路径的电路中，影子寄存器用于从外部源接收数据和传输数据。影子寄存器通过第一状态寄存器和第二状态寄存器与信号路径物理绝缘，第一状态寄存器将数据从信号路径传送到影子寄存器，第二状态寄存器在影子寄存器和信号路径之间传送数据。通过连接到第一和第二状态寄存器的相应输出的选择器来实现路径切换，并且响应用于仅从这些寄存器中的一个释放输出信号的控制信号。

4. 发明授权

US4967346A Universal microprocessor interface circuit 失效
标题翻译：通用微处理器接口电路
公开(公告)号：US4967346A
公开(公告)日：1990-10-30
申请号：US167598
申请日：1988-03-14
申请人： Philip Freidin
发明人： Philip Freidin
IPC分类号： G06F9/22 , G06F9/26 , G06F13/38
CPC分类号： G06F13/385 , G05B2219/2207
摘要： Interface circuitry (24) is provided which automatically detects which of two types of microprocessor is connected to the interface and configures the interface accordingly. A "type" flip-flop (36, 38) is initially set to expect a first type of microprocessor (10) and the interface is configured to expect a read and a write strobe. When a write cycle is performed by a second type (14) of microprocessor, the "type" flip-flop changes state and reconfigures the interface to expect a data strobe and a read/write indicator signal.

5. 发明申请

US20060162178A1 System for wireless local display of measurement data from electronic measuring tools and gauges 审中-公开
标题翻译：用于从电子测量工具和仪表无线本地显示测量数据的系统
公开(公告)号：US20060162178A1
公开(公告)日：2006-07-27
申请号：US11045943
申请日：2005-01-27
申请人： Philip Freidin
发明人： Philip Freidin
IPC分类号： G01B5/00
CPC分类号： G01B3/18 , H04Q9/00
摘要： A system for acquiring and displaying data in a measurement process includes a local display unit enabled for wireless data reception, and a measuring tool for acquiring measurement data, the tool being enabled for wireless data transmission. The system is characterized in that the acquired data is transmitted from the measuring tool to the local display unit and displayed thereon.
摘要翻译：用于在测量处理中获取和显示数据的系统包括能够进行无线数据接收的本地显示单元和用于获取测量数据的测量工具，该工具被启用用于无线数据传输。该系统的特征在于，所采集的数据从测量工具传送到本地显示单元并在其上显示。

6. 发明授权

US4835414A Flexible, reconfigurable terminal pin 失效
标题翻译：灵活，可重新配置的端子引脚
公开(公告)号：US4835414A
公开(公告)日：1989-05-30
申请号：US167670
申请日：1988-03-14
申请人： Philip Freidin
发明人： Philip Freidin
IPC分类号： G11C11/401 , G06F1/22 , H03K5/02 , H03K19/0175
CPC分类号： G06F1/22 , H03K5/026
摘要： A terminal pin (28) of an integrated circuit can be controlled in three ways to function as an input or an output pin. A logic circuit (16, 20, 23, 26) permits the pin to be synchronously enabled as an output terminal under software control. The circuit also permits the pin to be asynchronously enabled as an output terminal under control of a signal applied to another pin of the integrated circuit. The circuit also permits continuous control of the terminal as an output pin. Maskable bits stored in registers (18, 22) and configuration bits stored in register (25) affords additional flexibility in establishing which of the three ways the terminal pin wil be controlled.

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