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1. 发明授权

CN1009515B 半导体集成电路/系统失效
公开(公告)号：CN1009515B
公开(公告)日：1990-09-05
申请号：CN86106824
申请日：1986-09-10
申请人：皮尔金顿微电子技术有限公司
发明人：肯尼斯·奥斯汀
IPC分类号： H01L27/00 , H01L21/82
CPC分类号： H03K19/17748 , G06F17/5027 , H03K5/026 , H03K17/687 , H03K19/1733 , H03K19/1736 , H03K19/17704 , H03K19/17736 , H03K19/1778
摘要：每个可组合半导体集成电路的成品具有在分离位置上形成的多个逻辑电路，对于每个逻辑电路可选择的直接导通/不导通的连接通路，以自其输出到另一个逻辑电路的第一组输入而其输入又来自另一个逻辑电路的第二组输出的方式扩展，所有逻辑电路的全部组各不相同。描述了多功能的可组态输入/输出装置，还描述了采用可逆晶体管装置的重新组态数据处理系统。

2. 发明公开

CN86106824A 半导体集成电路/系统失效
公开(公告)号：CN86106824A
公开(公告)日：1987-06-03
申请号：CN86106824
申请日：1986-09-10
申请人：皮尔金顿微电子技术有限公司
发明人：肯尼斯·奥斯汀
IPC分类号： H01L27/00 , H01L21/70
CPC分类号： H03K19/17748 , G06F17/5027 , H03K5/026 , H03K17/687 , H03K19/1733 , H03K19/1736 , H03K19/17704 , H03K19/17736 , H03K19/1778
摘要：每个可组合半导体集成电路的成品具有在分离位置上形成的多个逻辑电路。对于每个逻辑电路，可选择的直接导通/不导通的连接通路，以自其输出到另一个逻辑电路的第一组输入而其输入又来自另一个逻辑电路的第二组输出的方式扩展。所有逻辑电路的全部组各不相同。描述了多功能的可组态输入/输出装置，还描述了采用可逆晶体管装置的重新组态数据处理系统。

3. 发明授权

US5412688A Process and circuit for detecting transmission using bi-directional differential links 失效
标题翻译：使用双向差分链路检测传输的过程和电路
公开(公告)号：US5412688A
公开(公告)日：1995-05-02
申请号：US199354
申请日：1994-02-18
申请人： Roland Marbot
发明人： Roland Marbot
IPC分类号： H04L29/00 , H03K5/02 , H04B1/58 , H04L5/14 , H04L25/02 , H04L29/14 , H04L5/16 , H04L27/00
CPC分类号： H03K5/026 , H04B1/58 , H04L5/1423
摘要： In certain bidirectional transmissions, differential links (L, L*) are used and transceivers (1) that furnish differential measurement signals (V, V*) representative of the transmission signals of the remote station are used. To reduce power consumption, the electrical power to the transceivers (1) may be interrupted during periods of inactivity. The method of the present invention consists in determining a threshold value which is intermediate in value between the maximum and minimum values that can be assumed by the measurement signals (V, V*), and furnishing a signal (VAL) representative of transmission activity resulting from the comparison between the measurement signals (V, V*) and the threshold value. The circuit for employing the method uses voltage comparators and may be an integrated circuit.
摘要翻译：在某些双向传输中，使用差分链路（L，L *），并且使用提供表示远程站的传输信号的差分测量信号（V，V *）的收发器（1）。为了降低功耗，收发器（1）的电力可能在不活动期间中断。本发明的方法在于确定在测量信号（V，V *）可以假设的最大值和最小值之间的中间值的阈值，并提供表示传输活动的信号（VAL）从测量信号（V，V *）和阈值之间的比较。采用该方法的电路使用电压比较器，并且可以是集成电路。

4. 发明授权

US3643223A Bidirectional transmission data line connecting information processing equipment 失效
标题翻译：双向传输数据线连接信息处理设备
公开(公告)号：US3643223A
公开(公告)日：1972-02-15
申请号：US3643223D
申请日：1970-04-30
申请人： HONEYWELL INF SYSTEMS
发明人： RUTH RICHARD L , SHELLY WILLIAM A
IPC分类号： H03K5/02 , H03K19/018 , H04L5/16 , G06F13/00
CPC分类号： H03K19/01831 , H03K5/026 , H04L5/16
摘要： A communicating port in an information processing device is equipped with an interconnected logic gating wherein the bidirectional transmission line is connected to an output of one logic gate and to an input of another logic gate. Series and parallel interconnections permit one bidirectional transmission line for each bit of information per device and per port of each device, respectively. A transmitter-receiver circuit pair is disclosed for the logic gating using current mode logic driving a grounded base amplifier.
摘要翻译：信息处理装置中的通信端口配备有互连逻辑门控，其中双向传输线连接到一个逻辑门的输出和另一个逻辑门的输入。串行和并行互连分别允许每个设备和每个设备的每个端口的每个位的信息的一个双向传输线。公开了一种使用驱动接地基放大器的电流模式逻辑的逻辑门控的发射机 - 接收机电路对。

5. 发明申请

WO1993009601A1 BIDIRECTIONAL BUS REPEATER 审中-公开
标题翻译：双向总线代理
公开(公告)号：WO1993009601A1
公开(公告)日：1993-05-13
申请号：PCT/US1992009285
申请日：1992-10-29
申请人： I-CUBE DESIGN SYSTEMS INC. , PiE DESIGN SYSTEMS INC.
发明人： I-CUBE DESIGN SYSTEMS INC. , PiE DESIGN SYSTEMS INC. , JENQ, Yih-Chyun , HORNG, Chi-Song , LOFSTROM, Keith
IPC分类号： H03K19/0175
CPC分类号： H03K5/026
摘要： A bidirectional bus repeater (10) includes two unidirectional bus repeaters (11, 13) connected for retransmitting signals in opposite directions between two buses (12, 14). When an external bus driver pulls either bus low, one of the unidirectional bus repeaters pulls the other bus low. When the external bus driver allows the bus to rise to the high logic level, the unidirectional bus repeater temporarily supplies a high charging current to the other bus to quickly pull it up. Each unidirectional bus repeater (11, 13) also generates signals indicating when it is actively pulling its output bus up or down and the indicating signals inhibit one unidirectional bus repeater from actively driving its output when the other unidirectional bus repeater is actively driving its output.

6. 发明授权

EP0094238B1 Transistor output circuit 失效
标题翻译：晶体管输出电路
公开(公告)号：EP0094238B1
公开(公告)日：1987-09-09
申请号：EP83302611.5
申请日：1983-05-09
申请人： NEC CORPORATION
发明人： Morito, Hiroshi
IPC分类号： H03K19/094 , H03K5/02
CPC分类号： H03K19/215 , H03K5/023 , H03K5/026 , H03K19/018507

7. 发明公开

EP0219221A2 Semi-conductor integrated circuits 失效
标题翻译：半导体集成电路。
公开(公告)号：EP0219221A2
公开(公告)日：1987-04-22
申请号：EP86306966.2
申请日：1986-09-10
申请人： Pilkington Micro-Electronics Limited
发明人： Austin, Kenneth
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , G06F17/5027 , H03K5/026 , H03K17/687 , H03K19/1733 , H03K19/1736 , H03K19/17704 , H03K19/17736 , H03K19/1778
摘要： Configurable semiconductor integrated circuits as-made each have a plurality of logic circuits formed at discrete sites (10S). For each logic circuit, direct selectably conducting/non- conducting connection paths (14A,B,C,F) extend from its output to input of a first set of other logic circuits and to its inputs from outputs of a second set of other logic circuits. All of the sets for all of the logic circuits are each different. Other direct connection paths (50R,50C) are selectably connectable to inputs (14D,E) and outputs (52G,H) of the logic circuits. Selection can be irreversible (Figure 8) or reversible (Figures 9, 10, 11, 18) and involves coincident signal addressing (22R,C) of the sites (105) and coded configuring ofthe paths at that site. Reversible selection can beviafield effect transistors or bipolar transistors and can be at or near normal logic signal levels and speeds (Figures 11 and 18). Versatile configurable input/output arrangements are described (Figures 13-16), also reconfigurable data processing systems using the reversible transistor provisions (Figures 20-23).

8. 发明授权

US5559456A Sensing circuit unit for a dynamic circuit 失效
标题翻译：用于动态电路的感应电路单元
公开(公告)号：US5559456A
公开(公告)日：1996-09-24
申请号：US106551
申请日：1993-08-16
申请人： Tsuguyasu Hatsuda
发明人： Tsuguyasu Hatsuda
IPC分类号： G11C7/06 , H03K5/02 , H03F3/45
CPC分类号： G11C7/067 , H03K5/026
摘要： In the present invention, there are disposed (i) a P-channel MOSFET for detecting variations of the voltage level of a data line to supply an electric current, and (ii) a current mirror circuit to which an electric current from the P-channel MOSFET is entered as a reference current and of which output current terminal is connected to the data line. When the data line is lowered in voltage level so that an electric current flows from the P-channel MOSFET to the current mirror circuit, an output current of the current mirror circuit flows to the drain of an N-channel MOSFET, so that the data line is electrically discharged. Thus, there is achieved a sensing circuit unit which is suitably used for a dynamic circuit and which can detect, at a high speed, variations of the voltage level of the data line as precharged.
摘要翻译：在本发明中，设置（i）用于检测数据线的电压电平的变化以提供电流的P沟道MOSFET，以及（ii）电流镜电路，其中来自P- 通道MOSFET作为参考电流输入，其输出电流端子连接到数据线。当数据线在电压电平下降使得电流从P沟道MOSFET流到电流镜电路时，电流镜电路的输出电流流向N沟道MOSFET的漏极，使得数据线线路电气放电。因此，实现了适合用于动态电路的感测电路单元，并且可以高速检测预充电的数据线的电压电平的变化。

9. 发明授权

US5532630A Receiver circuit with a bus-keeper feature 失效
标题翻译：具有总线保护功能的接收器电路
公开(公告)号：US5532630A
公开(公告)日：1996-07-02
申请号：US281509
申请日：1994-07-27
申请人： Charles D. Waggoner , Richard J. Blumberg , Gary B. Kotzur
发明人： Charles D. Waggoner , Richard J. Blumberg , Gary B. Kotzur
IPC分类号： G06F3/00 , H03K3/356 , H03K5/02 , H03K19/0175 , H04L29/10 , H03K3/00 , H03K17/16
CPC分类号： H03K5/026 , H03K3/356104
摘要： A bidirectional input/output buffer is disclosed, where the receiver includes complementary bus keeper transistors. The keeper transistors are of opposite conductivity types, and have their gates coupled to the output of a receiver inverter. The keeper transistors thus reinforce the driven data state at the input of the receiver, in CMOS latch fashion, and hold the prior data state thereon after the driving output driver is in tristate. The keeper transistors have significantly weaker drive characteristics than the other receiver transistors, and than typical output drivers, so that the keeper transistors can be easily overdriven with the next data state, if different. In addition, the source/drain resistance of the keeper transistors is also preferably quite high, so that the power dissipation on switching is relatively low. These characteristics are readily achievable by providing relatively long channel lengths for the keeper transistors, relative to other transistors in the circuit.
摘要翻译：公开了一种双向输入/输出缓冲器，其中接收器包括互补的总线保持器晶体管。保持器晶体管具有相反的导电类型，并且其栅极耦合到接收器反相器的输出。保持器晶体管因此以CMOS锁存方式加强了接收器输入处的驱动数据状态，并且在驱动输出驱动器处于三态之后保持其先前的数据状态。保持器晶体管的驱动特性明显弱于其他接收晶体管，而不是典型的输出驱动器，因此如果不同，保持晶体管可以容易地过渡到下一个数据状态。此外，保持晶体管的源极/漏极电阻也优选相当高，使得开关时的功率耗散相对较低。通过相对于电路中的其它晶体管为保持器晶体管提供相对长的沟道长度，可以容易地实现这些特性。

10. 发明授权

US5202593A Bi-directional bus repeater 失效
标题翻译：双向总线中继器
公开(公告)号：US5202593A
公开(公告)日：1993-04-13
申请号：US785299
申请日：1991-10-30
申请人： Thomas B. Huang , Yih-Chyun Jenq , Keith Lofstrom
发明人： Thomas B. Huang , Yih-Chyun Jenq , Keith Lofstrom
IPC分类号： H03K19/0175 , H03K5/02 , H04L5/16
CPC分类号： H03K5/026
摘要： A bi-directional bus repeater includes two unidirectional bus repeaters connected for retransmitting signals in opposite directions between two buses. When an external bus driver pulls either bus low, one of the unidirectional bus repeaters pulls the other bus low. When the external bus driver allows the bus to rise to the high logic level, the unidirectional bus repeater temporarily supplies a high charging current to the other bus to quickly pull it up. Each unidirectional bus repeater also generates signals indicating when it is actively pulling its output bus up or down and the indicating signals inhibit one unidirectional bus repeater from actively driving its output when the other unidirectional bus repeater is actively driving its output.
摘要翻译：双向总线中继器包括两个单向总线中继器，用于在两条总线之间的相反方向重新发送信号。当外部总线驱动器将总线拉低时，其中一个单向总线中继器将另一个总线拉低。当外部总线驱动器允许总线上升到高逻辑电平时，单向总线中继器临时向另一个总线提供高充电电流，以快速将其拉高。每个单向总线中继器还产生指示何时正在向上或向下拉动其输出总线的信号，并且当另一个单向总线中继器正在主动驱动其输出时，指示信号禁止一个单向总线中继器主动驱动其输出。

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