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1. 发明授权

US09479866B2 Microphone array with daisy-chain summation 有权
标题翻译：带菊花链求和的麦克风阵列
公开(公告)号：US09479866B2
公开(公告)日：2016-10-25
申请号：US13428496
申请日：2012-03-23
申请人： Robert Adams , David Hossack , Benjamin Vigoda , Eric Nestler , Mira Wilczek
发明人： Robert Adams , David Hossack , Benjamin Vigoda , Eric Nestler , Mira Wilczek
IPC分类号： H04R3/00
CPC分类号： H04R3/005 , H04R2499/13
摘要： Microphone stages in a microphone array may be coupled together in a daisy chain. Each stage may include a microphone, an analog to digital converter, a decimation unit, a receiver, an adder, and a transmitter. The converter may convert analog audio microphone signals into digital codes that may be decimated. The adder may add decimated digital codes in each stage to a cumulative sum of decimated digital codes from prior stages. This new sum may be transmitted to the next microphone stage, where the adder may add the decimated digital codes from that stage to the cumulative sum. A serial interface may be used to connect the transmitters and receivers of each of the stages. The serial interface may be used to transmit the cumulative sum of decimated digital codes between the stages. The serial interface may also be used to transmit configuration data between the stages.
摘要翻译：麦克风阵列中的麦克风级可以以菊花链耦合在一起。每个阶段可以包括麦克风，模数转换器，抽取单元，接收器，加法器和发射器。转换器可将模拟音频麦克风信号转换为可能被抽取的数字代码。加法器可以将每个级中的抽取的数字代码添加到来自前一级的抽取的数字代码的累积和。这个新的和可以传送到下一个麦克风阶段，其中加法器可以将从该阶段抽取的数字代码添加到累积和。可以使用串行接口连接每个级的发射机和接收机。串行接口可以用于在级之间传送抽取的数字代码的累加和。串行接口也可用于在各个级之间传输配置数据。

2. 发明授权

US08799346B2 Belief propagation processor 有权
标题翻译：信仰传播处理器
公开(公告)号：US08799346B2
公开(公告)日：2014-08-05
申请号：US13079204
申请日：2011-04-04
申请人： David Reynolds , Benjamin Vigoda
发明人： David Reynolds , Benjamin Vigoda
IPC分类号： G06G7/00
CPC分类号： H03M13/1111 , G06G7/122 , G06G7/1942 , H03M13/1137 , H03M13/1188 , H03M13/6597
摘要： A processor includes a first memory module for storing a first set of storage values each representing a respective input, and a second memory module for storing a second set of storage values in analog form. An analog module is coupled to the first and the second memory modules. The analog module is configured to, in each operation cycle of at least one iteration, update at least some of the second set of storage values based on the first and the second sets of storage values. An output module is for generating a set of outputs from at least some of the second set of storage values.
摘要翻译：处理器包括：第一存储器模块，用于存储每个表示相应输入的第一组存储值;以及第二存储器模块，用于以模拟形式存储第二组存储值。模拟模块耦合到第一和第二存储器模块。模拟模块被配置为在至少一次迭代的每个操作周期中，基于第一和第二组存储值来更新第二组存储值中的至少一些。输出模块用于从第二组存储值中的至少一些产生一组输出。

3. 发明授权

US08344924B2 Analog signal conversion 有权
标题翻译：模拟信号转换
公开(公告)号：US08344924B2
公开(公告)日：2013-01-01
申请号：US13095188
申请日：2011-04-27
申请人： Benjamin Vigoda , Jeffrey Bernstein , Alexander Alexeyev , William Bradley , Theophane Weber
发明人： Benjamin Vigoda , Jeffrey Bernstein , Alexander Alexeyev , William Bradley , Theophane Weber
IPC分类号： H03M1/12
CPC分类号： G06J1/00
摘要： An approach to converting an analog value based on a partition of an input range produces probabilities that the input is found within each of the regions based, for example, on a noisy version of the input. In some examples, iterative and/or pipelined application of comparison circuitry is used to accumulate a set of analog representations of the output probabilities. The circuitry can be adapted or configured according to the characteristics of the degradation (e.g., according to the variance of an additive noise) and/or prior information about the distribution of the clean input (e.g., a distribution over a discrete set of exemplar values, uniformly distributed etc.).
摘要翻译：基于输入范围的分区来转换模拟值的方法产生在例如基于输入的噪声版本的情况下在每个区域内发现输入的概率。在一些示例中，使用比较电路的迭代和/或流水线应用来累积输出概率的一组模拟表示。电路可以根据劣化的特性进行调整或配置（例如，根据加性噪声的变化）和/或关于干净输入分布的先前信息（例如，在离散的一组样本值上的分布，均匀分布等）。

4. 发明授权

US06724805B1 Nonlinear dynamic system for spread spectrum code generation and acquisition 有权
标题翻译：用于扩频码生成和采集的非线性动态系统
公开(公告)号：US06724805B1
公开(公告)日：2004-04-20
申请号：US09713644
申请日：2000-11-15
申请人： Benjamin Vigoda
发明人： Benjamin Vigoda
IPC分类号： H04B169
CPC分类号： H04B1/7075
摘要： Nonlinear dynamic systems for generating and acquiring a spread spectrum signal pseudo-random noise (PN) signal are disclosed. An actuating signal is delayed by a first and second period to produce delayed actuating signals. A continuous, nonlinear function is applied to input that corresponds to the delayed actuating signals to produce an output signal. The function has values that correspond to the binary integer values of the mod 2 addition function of a linear feedback shift register, and a non-zero slope at those values. The output signal becomes a PN signal over time when it is fed back to the actuating signal. The output signal synchronizes with a spread spectrum reference input signal when it is superposed on the reference input signal to produce the actuating signal. The system may be incorporated into a transmitter or a receiver, either of which may be part of a larger communication system.
摘要翻译：公开了用于产生和获取扩频信号伪随机噪声（PN）信号的非线性动态系统。致动信号被延迟第一和第二周期以产生延迟的致动信号。连续的非线性函数被应用于对应于延迟的致动信号的输入以产生输出信号。该函数具有对应于线性反馈移位寄存器的mod 2加法函数的二进制整数值以及在这些值的非零斜率的值。当输出信号反馈到启动信号时，输出信号随时间变为PN信号。当输出信号叠加在参考输入信号上时，输出信号与扩频参考输入信号同步以产生致动信号。该系统可以并入到发射机或接收机中，其中任何一个可以是更大的通信系统的一部分。

5. 发明申请

US20140223439A1 SUPERSCALAR CONTROL FOR A PROBABILITY COMPUTER 审中-公开
标题翻译：一个概率计算机的超级控制
公开(公告)号：US20140223439A1
公开(公告)日：2014-08-07
申请号：US14130403
申请日：2011-02-22
申请人： Benjamin Vigoda
发明人： Benjamin Vigoda
IPC分类号： G06F9/48
CPC分类号： G06F9/4843 , G06N7/005
摘要： A method of executing operations in parallel in a probability processing system includes providing a probability processor for executing said operations; and providing a scheduler for identifying, from said operations, those operations that can be executed in parallel. Providing the scheduler includes compiling code written in a probability programming language, that includes both modeling instructions and instructions for scheduling.
摘要翻译：在概率处理系统中并行执行操作的方法包括提供用于执行所述操作的概率处理器; 以及提供调度器，用于从所述操作中识别可以并行执行的那些操作。提供调度器包括编译以概率编程语言编写的代码，其包括建模指令和调度指令。

6. 发明授权

US08792602B2 Mixed signal stochastic belief propagation 有权
标题翻译：混合信号随机信念传播
公开(公告)号：US08792602B2
公开(公告)日：2014-07-29
申请号：US13032520
申请日：2011-02-22
申请人： Jeffrey Bernstein , Benjamin Vigoda , David Reynolds , Alexander Alexeyev , William Bradley
发明人： Jeffrey Bernstein , Benjamin Vigoda , David Reynolds , Alexander Alexeyev , William Bradley
IPC分类号： H04L7/00 , H03M13/11 , H03M13/00
CPC分类号： H03M13/6597 , H03M13/1111
摘要： A processor implements a network of functional nodes and communication paths between the nodes. The processor includes a plurality of circuit implementations of the functional nodes of the processor; and a plurality of signal paths implementing the communication paths linking the circuit implementations of the nodes. At least some of the signal paths are configured to pass signal values represented according to temporal patterns of signal levels on the signal paths. The processor also includes a plurality of circuit components for conversion between a signal value represented as a signal level (e.g., voltage or current level) and a signal value represented as a temporal pattern.
摘要翻译：处理器实现节点之间的功能节点和通信路径的网络。处理器包括处理器的功能节点的多个电路实现; 以及实现链接节点的电路实现的通信路径的多个信号路径。至少一些信号路径被配置为传递根据信号路径上的信号电平的时间模式表示的信号值。处理器还包括用于在表示为信号电平（例如，电压或电流电平）的信号值和表示为时间模式的信号值之间进行转换的多个电路部件。

7. 发明授权

US08627246B2 Implementation of factor graphs 有权
标题翻译：因子图的实现
公开(公告)号：US08627246B2
公开(公告)日：2014-01-07
申请号：US13006060
申请日：2011-01-13
申请人： Shawn Hershey , Benjamin Vigoda
发明人： Shawn Hershey , Benjamin Vigoda
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： The process of implementing a belief propagation network in software and/or hardware can begin with a factor-graph-designer who designs a factor graph that implements that network. A development system provides a user with a way to specify a factor graph at a high or abstract level, and then solve the factor graph, or make an instance of the factor graph in software and/or hardware based on the specification. Factor graphs enable designers to create a graphical model of complicated belief propagation networks such as Markov chains, hidden Markov models, and Bayesian networks.
摘要翻译：在软件和/或硬件中实现信任传播网络的过程可以从设计实现该网络的因子图的因子图设计者开始。开发系统为用户提供了一种以高或抽象级别指定因子图的方式，然后根据规范解决因子图，或者在软件和/或硬件中制作因子图的实例。因子图使设计人员能够创建一个复杂信念传播网络的图形模型，如马尔科夫链，隐马尔可夫模型和贝叶斯网络。

8. 发明授权

US08458114B2 Analog computation using numerical representations with uncertainty 有权
标题翻译：使用具有不确定性的数值表示的模拟计算
公开(公告)号：US08458114B2
公开(公告)日：2013-06-04
申请号：US12716155
申请日：2010-03-02
申请人： Benjamin Vigoda , William Bradley , Shawn Hershey , Jeffrey Bernstein
发明人： Benjamin Vigoda , William Bradley , Shawn Hershey , Jeffrey Bernstein
IPC分类号： G06F9/44 , G06N7/02 , G06N7/06
CPC分类号： G06N7/005
摘要： Some general aspects relate to systems and methods of analog computation using numerical representation with uncertainty. For example, a specification of a group of variables is accepted, with each variable having a set of at least N possible values. The group of variables satisfies a set of one or more constraints, and each variable is specified as a decomposition into a group of constituents, with each constituent having a set of M (e.g., M
摘要翻译：一些一般方面涉及使用具有不确定性的数值表示的模拟计算的系统和方法。例如，接受一组变量的规范，每个变量具有至少N个可能值的集合。变量组满足一个或多个约束的集合，并且每个变量被指定为分组成一组成分，其中每个组成部分具有一组M（例如，M

9. 发明申请

US20130094298A1 STORAGE DEVICES WITH SOFT PROCESSING 有权
标题翻译：具有软处理的存储设备
公开(公告)号：US20130094298A1
公开(公告)日：2013-04-18
申请号：US13471816
申请日：2012-05-15
申请人： Benjamin Vigoda , Eric Nestler , Jeffrey Bernstein , David Reynolds , Alexander Alexeyev , Jeffrey Venuti , William Bradley , Vladimir Ziatkovic
发明人： Benjamin Vigoda , Eric Nestler , Jeffrey Bernstein , David Reynolds , Alexander Alexeyev , Jeffrey Venuti , William Bradley , Vladimir Ziatkovic
IPC分类号： G11C7/00 , G11C16/04 , G11C11/24
CPC分类号： G11C7/00 , G11C7/1006 , G11C7/16 , G11C11/24 , G11C11/5642 , G11C16/04 , G11C27/005 , G11C29/00
摘要： A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.
摘要翻译：存储装置包括具有一组存储元件的存储阵列。每个存储元件可以写入一组离散的物理状态。读取电路选择一个或多个存储元件，并为每个选定的存储元件生成表示所选存储元件的物理状态的模拟信号。信号处理电路处理模拟信号以产生多个输出，其中每个输出表示所选择的存储元件与离散的物理状态集合中的一个或多个的不同子集的关联程度。

10. 发明申请

US20100246289A1 STORAGE DEVICES WITH SOFT PROCESSING 有权
公开(公告)号：US20100246289A1
公开(公告)日：2010-09-30
申请号：US12537081
申请日：2009-08-06
申请人： Benjamin Vigoda , Jeffrey Bernstein , Jeffrey Venuti , David Reynolds , Alexander Alexeyev
发明人： Benjamin Vigoda , Jeffrey Bernstein , Jeffrey Venuti , David Reynolds , Alexander Alexeyev
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C7/1006 , G11C7/16 , G11C11/24 , G11C11/5642 , G11C16/04 , G11C27/005 , G11C29/00
摘要： A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

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