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1. 发明授权

US06940807B1 Method and apparatus for a X-DSL communication processor 失效
标题翻译：用于X-DSL通信处理器的方法和装置
公开(公告)号：US06940807B1
公开(公告)日：2005-09-06
申请号：US09699193
申请日：2000-10-26
申请人： Behrooz Rezvani , Avadhani Shridhar , Raminder S. Bajwa , Tiruvur R. Ramesh , Masoud Eskandari , Firooz Massoudi , Sam Heidari , Omprakash S. Sarmaru , Sridhar Begur
发明人： Behrooz Rezvani , Avadhani Shridhar , Raminder S. Bajwa , Tiruvur R. Ramesh , Masoud Eskandari , Firooz Massoudi , Sam Heidari , Omprakash S. Sarmaru , Sridhar Begur
IPC分类号： H04J11/00
CPC分类号： G06F17/142 , H04L27/2628 , H04L27/265
摘要： The current invention provides a DSP which accommodates multiple current X-DSL protocols and is further configurable to support future protocols. The DSP is implemented with shared and dedicated hardware components on both the transmit and receive paths. The DSP implements both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) portions across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session. The DSP offers the speed associated with hardware implementation of the transforms and the flexibility of a software only implementation. Traffic flow is regulated in the chip using a packet based schema in which each packet is associated with a specific channel of upstream and downstream data. Header and control information in each packet is used to govern the processing of each packet as it moves along either the transmit path or receive path. The DSP of the current invention may advantageously be utilized in fields other than communications, such as: medical and other imaging, seismic analysis, radar and other military applications, pattern recognition, signal processing etc. The present invention provides a signal processing architecture that supports scalability of CO/DLC/ONU resources, and allows a significantly more flexible hardware response to the evolving X-DSL standards without over committing of hardware resources. As standards evolve hardware may be reconfigured to support the new standards.
摘要翻译：本发明提供一种DSP，其容纳多个当前的X-DSL协议，并且可进一步配置以支持未来的协议。 DSP在传输和接收路径上都具有共享和专用硬件组件。 DSP在宽范围的采样大小和X-DSL协议上实现离散傅立叶变换（DFT）和离散傅立叶逆变换（IDFT）部分。每个具有不同的X-DSL协议的多个信道可以在同一个会话中处理。 DSP提供与转换的硬件实现相关的速度和仅用于软件的实现的灵活性。使用基于分组的模式在芯片中调整流量流，其中每个分组与上游和下游数据的特定信道相关联。每个数据包中的报头和控制信息用于控制每个数据包沿着发送路径或接收路径移动时的处理。本发明的DSP可有利地用于通信以外的领域，例如：医疗和其他成像，地震分析，雷达和其他军事应用，模式识别，信号处理等。本发明提供一种信号处理架构，其支持 CO / DLC / ONU资源的可扩展性，并且允许对演进的X-DSL标准的显着更灵活的硬件响应，而不必超过硬件资源。随着标准的发展，硬件可能被重新配置以支持新的标准。

2. 发明授权

US08065504B2 Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor 有权
标题翻译：使用由指令地址索引的片上和片外查找表来控制处理器中的指令执行
公开(公告)号：US08065504B2
公开(公告)日：2011-11-22
申请号：US11004729
申请日：2004-12-02
申请人： John S. Yates, Jr. , David L. Reese , Paul H. Hohensee , Korbin S. Van Dyke , Shalesh Thusoo , Tiruvur R. Ramesh
发明人： John S. Yates, Jr. , David L. Reese , Paul H. Hohensee , Korbin S. Van Dyke , Shalesh Thusoo , Tiruvur R. Ramesh
IPC分类号： G06F9/30
CPC分类号： G06F9/45533
摘要： A microprocessor chip has instruction pipeline circuitry, and instruction classification circuitry that classifies instructions as they are executed into a small number of classes and records a classification code value. An on-chip table has entries corresponding to a range of addresses of a memory and designed to hold a statistical assessment of a value of consulting an off-chip table in a memory of the computer. Lookup circuitry is designed to fetch an entry from the on-chip table as part of the basic instruction processing cycle of the microprocessor. A mask has a value set at least in part by a timer. The instruction pipeline circuitry is controlled based on the value of the on-chip table entry corresponding to the address of instructions processed, the current value of the mask, the recorded classification code, and the off-chip table.
摘要翻译：微处理器芯片具有指令流水线电路和指令分类电路，它们将执行的指令分类为少量类并记录分类代码值。片上表具有对应于存储器的一系列地址的条目，并且被设计为保持在计算机的存储器中查看片外表的值的统计评估。查找电路被设计为从微处理器的基本指令处理周期的一部分获取片上表格中的条目。掩码至少部分由定时器设置的值。基于与所处理的指令的地址，掩码的当前值，记录的分类代码和片外表相对应的片上表项的值来控制指令流水线电路。

3. 发明授权

US06651159B1 Floating point register stack management for CISC 有权
标题翻译： CISC浮点寄存器堆栈管理
公开(公告)号：US06651159B1
公开(公告)日：2003-11-18
申请号：US09449956
申请日：1999-11-29
申请人： Tiruvur R. Ramesh , Sanjay Mansingh , Korbin Van Dyke
发明人： Tiruvur R. Ramesh , Sanjay Mansingh , Korbin Van Dyke
IPC分类号： G06F9455
CPC分类号： G06F9/45533 , G06F9/30105 , G06F9/30112 , G06F9/30123 , G06F9/30134 , G06F9/30174
摘要： A floating point register stack for a processor combines a plurality of two general purpose registers to form a register stack for x86 instructions and leaves the remaining general purpose registers for native instructions of the processor. By mapping x86 sources into the stack of two general purpose registers and operating x86 instructions on the x86 stack, the register stack for the processor is able to support both the processor's native instruction set and the x86 instruction set without increasing the size of the register stack.
摘要翻译：用于处理器的浮点寄存器堆栈组合多个两个通用寄存器以形成用于x86指令的寄存器堆栈，并留下剩余的通用寄存器用于处理器的本机指令。通过将x86源映射到x86堆栈中的两个通用寄存器堆栈和操作x86指令，处理器的寄存器堆栈能够支持处理器的本地指令集和x86指令集，而不增加寄存器堆栈的大小。

4. 发明授权

US08074055B1 Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code 有权
标题翻译：当执行从第一架构代码流向第二架构代码时，更改处理器的数据存储约定
公开(公告)号：US08074055B1
公开(公告)日：2011-12-06
申请号：US09385394
申请日：1999-08-30
申请人： John S. Yates, Jr. , David L. Reese , Korbin S. Van Dyke , Tiruvur R. Ramesh , Paul H. Hohensee
发明人： John S. Yates, Jr. , David L. Reese , Korbin S. Van Dyke , Tiruvur R. Ramesh , Paul H. Hohensee
IPC分类号： G06F9/30
CPC分类号： G06F9/3005 , G06F9/30174 , G06F9/3804
摘要： A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction's page.
摘要翻译：一台电脑。处理器流水线交替执行针对第一和第二不同计算机体系结构编码的编码或编码以执行第一和第二不同处理惯例的指令。存储器存储由处理器流水线执行的指令，存储器被划分为页面以供虚拟存储器管理器管理，存储器的单个地址空间具有第一和第二页面。存储器单元从存储器中取出指令以由流水线执行，并且获取存储的指示符元素，其与要获取指令的单个地址空间的相应存储器页相关联。每个指示符元素被设计为存储两个不同的计算机体系结构和/或执行约定中的哪一个的指示，在该约定下，相关联的页面的指令数据将由处理器管线执行。存储器单元和/或处理器流水线将来自第一页面的执行流程（其相关联的指示符元素指示第一架构或执行约定）识别到第二页面，其第二页面的相关联的指示符元素指示第一个架构或执行约定。响应于识别，处理器流水线的处理模式或存储器的存储内容适应于执行由该指令页面所对应的指标元素所指示的体系结构和/或规定的指令。

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