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1. 发明申请

US20070212889A1 Trim process for critical dimension control for integrated circuits 失效
标题翻译：用于集成电路的关键尺寸控制的修整过程
公开(公告)号：US20070212889A1
公开(公告)日：2007-09-13
申请号：US11372825
申请日：2006-03-09
申请人： Mirzafer Abatchev , Krupakar Subramanian , Baosuo Zhou
发明人： Mirzafer Abatchev , Krupakar Subramanian , Baosuo Zhou
IPC分类号： H01L21/467
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139
摘要： Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.
摘要翻译：公开了采用用于集成电路的关键尺寸控制的修整工艺的衬底的蚀刻方法。在一个实施例中，蚀刻方法包括在目标层上提供第一硬掩模层; 在第一硬掩模层上提供第二硬掩模层; 在所述第二硬掩模层上提供光致抗蚀剂层; 在光致抗蚀剂层中形成图案; 将图案转移到第二硬掩模层中; 以及在所述第二硬掩模层的顶部上用所述光致抗蚀剂层修剪所述第二硬掩模层。第二硬掩模层的顶表面由光致抗蚀剂保护，并且衬底在修整蚀刻期间被上覆的第一硬掩模层保护，因此可以是侵蚀性的。

2. 发明申请

US20070123050A1 Etch process used during the manufacture of a semiconductor device and systems including the semiconductor device 审中-公开
标题翻译：在制造半导体器件期间使用的蚀刻工艺和包括半导体器件的系统
公开(公告)号：US20070123050A1
公开(公告)日：2007-05-31
申请号：US11272980
申请日：2005-11-14
申请人： Baosuo Zhou , Mirzafer Abatchev , Krupakar Subramanian
发明人： Baosuo Zhou , Mirzafer Abatchev , Krupakar Subramanian
IPC分类号： C23F1/00 , H01L29/04 , H01L21/461 , B44C1/22 , H01L31/036
CPC分类号： H01L21/31144 , H01L21/02126 , H01L21/31116 , H01L21/31122 , H01L21/3146 , H01L27/10852 , H01L28/84
摘要： A carbon or carbon-containing underlayer, which is used as a mask, is patterned using a process comprising, in one specific embodiment, boron trichloride and oxygen under specified processing conditions to etch the underlayer. The underlayer is then used as a mask to etch a layer below the underlayer, such as a semiconductor wafer or a layer formed as part of a semiconductor wafer substrate assembly. Various processing conditions are described, as is the formation of various features using embodiments of the inventive process.
摘要翻译：用作掩模的含碳或碳的底层使用包括在一个具体实施方案中的三氯化硼和氧气在特定加工条件下蚀刻底层的方法进行图案化。然后将底层用作掩模以蚀刻底层以下的层，例如半导体晶片或形成为半导体晶片衬底组件的一部分的层。描述了各种处理条件，使用本发明方法的实施例形成各种特征。

3. 发明申请

US20070049032A1 Protective coating for planarization 有权
标题翻译：用于平坦化的保护涂层
公开(公告)号：US20070049032A1
公开(公告)日：2007-03-01
申请号：US11219604
申请日：2005-09-01
申请人： Mirzafer Abatchev , David Wells , Baosuo Zhou , Krupakar Subramanian
发明人： Mirzafer Abatchev , David Wells , Baosuo Zhou , Krupakar Subramanian
IPC分类号： H01L21/302
CPC分类号： H01L21/31051 , H01L21/0337 , H01L21/306 , H01L21/30625 , H01L21/31055 , H01L21/31111 , H01L21/31144 , Y10T29/49128 , Y10T29/49146 , Y10T29/49151 , Y10T29/49155 , Y10T29/49171 , Y10T29/49172 , Y10T29/49176 , Y10T29/4922 , Y10T29/49224
摘要： Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
摘要翻译：可以使用各种图案转移和蚀刻步骤来产生特征。传统的光刻步骤可以与俯仰减小技术结合使用，以形成可以被整合成单一层的交叉细长特征的叠加的俯仰减小图案。公开了使用填充层和保护层的平面化技术。具有不同高度的集成电路的部分可以被蚀刻到公共平面。

4. 发明申请

US20070066068A1 Method of depositing a layer comprising silicon, carbon, and flourine onto a semiconductor substrate 失效
标题翻译：将包含硅，碳和矾土的层沉积到半导体衬底上的方法
公开(公告)号：US20070066068A1
公开(公告)日：2007-03-22
申请号：US11601362
申请日：2006-11-16
申请人： Mirzafer Abatchev , Krupakar Subramanian
发明人： Mirzafer Abatchev , Krupakar Subramanian
IPC分类号： C03C25/68 , B01F17/00 , H01L21/311 , H01L21/302
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/3148
摘要： The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and fluorine onto a semiconductor substrate. In one implementation, a method of etching includes forming a masking feature projecting from a substrate. The feature has a top, opposing sidewalls, and a base. A layer comprising SixCyFz is deposited over the feature, where “x” is from 0 to 0.2, “y” is from 0.3 to 0.9, and “z” is from 0.1 to 0.6. The SixCyFz—comprising layer and upper portions of the feature opposing sidewalls are etched effective to laterally recess such upper portions proximate the feature top relative to lower portions of the feature opposing sidewalls proximate the feature base. After such etching of the SixCyFz—comprising layer and such etching of upper portions of the feature sidewalls, the substrate is etched using the masking feature as a mask.
摘要翻译：本发明包括蚀刻衬底的方法，在衬底上形成特征的方法，以及将包含硅，碳和氟的层沉积到半导体衬底上的方法。在一个实施方案中，蚀刻方法包括形成从基板突出的掩模特征。该特征具有顶部，相对的侧壁和基部。在特征上沉积包含Si x Si x F z的层，其中“x”为0至0.2，“y”为 0.3〜0.9，“z”为0.1〜0.6。有意义的是，具有相同特征的Si层和顶部相对侧壁的上部被有效地横向凹入靠近特征是相对于靠近特征基部的相对侧壁的特征的下部。在这种蚀刻Si x SiCl 3 Z z-x元素层并蚀刻特征侧壁的上部之后，蚀刻基板使用屏蔽功能作为掩码。

5. 发明申请

US20070049028A1 Nanoimprint lithography template techniques for use during the fabrication of a semiconductor device and systems including same 失效
标题翻译：在制造半导体器件期间使用的纳米压印光刻模板技术及包括其的系统
公开(公告)号：US20070049028A1
公开(公告)日：2007-03-01
申请号：US11214684
申请日：2005-08-30
申请人： Krupakar Subramanian , Mirzafer Abatchev
发明人： Krupakar Subramanian , Mirzafer Abatchev
IPC分类号： B44C1/22 , B05C1/00 , H01L21/302
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00 , Y10S977/887 , Y10S977/888
摘要： A method for forming a template useful for nanoimprint lithography comprises forming at least one pillar which provides a topographic feature extending from a template base. At least one conformal pattern layer and one conformal spacing layer, and generally a plurality of alternating pattern layers and spacing layers, are formed over the template base and pillar. A planarized filler layer is formed over the pattern and spacing layers, then the filler, the spacing layer and the pattern layer are partially removed, for example using mechanical polishing, to expose the pillar. One or more etches are performed to remove at least a portion of the pillar, the filler, and the spacing layer to result in the pattern layer protruding from the spacing layer and providing the template pattern.
摘要翻译：用于形成用于纳米压印光刻的模板的方法包括形成提供从模板基底延伸的地形特征的至少一个柱。在模板基底和柱上方形成至少一个共形图案层和一个共形间隔层，以及通常多个交替图案层和间隔层。在图案和间隔层之上形成平坦化的填充层，然后例如使用机械抛光部分去除填料，间隔层和图案层以暴露柱。执行一个或多个蚀刻以去除柱，填料和间隔层的至少一部分，以导致图案层从间隔层突出并提供模板图案。

6. 发明申请

US20070042605A1 METHOD OF ETCHING A SUBSTRATE AND METHOD OF FORMING A FEATURE ON A SUBSTRATE 有权
标题翻译：蚀刻基板的方法和在基板上形成特征的方法
公开(公告)号：US20070042605A1
公开(公告)日：2007-02-22
申请号：US11206414
申请日：2005-08-18
申请人： Mirzafer Abatchev , Krupakar Subramanian
发明人： Mirzafer Abatchev , Krupakar Subramanian
IPC分类号： C03C25/68 , C03C15/00 , H01L21/311 , H01L21/302
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/3148
摘要： The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and fluorine onto a semiconductor substrate. In one implementation, a method of etching includes forming a masking feature projecting from a substrate. The feature has a top, opposing sidewalls, and a base. A layer comprising SixCyFz is deposited over the feature, where “x” is from 0 to 0.2, “y” is from 0.3 to 0.9, and “z” is from 0.1 to 0.6. The SixCyFz-comprising layer and upper portions of the feature opposing sidewalls are etched effective to laterally recess such upper portions proximate the feature top relative to lower portions of the feature opposing sidewalls proximate the feature base. After such etching of the SixCyFz-comprising layer and such etching of upper portions of the feature sidewalls, the substrate is etched using the masking feature as a mask.
摘要翻译：本发明包括蚀刻衬底的方法，在衬底上形成特征的方法，以及将包含硅，碳和氟的层沉积到半导体衬底上的方法。在一个实施方案中，蚀刻方法包括形成从基板突出的掩模特征。该特征具有顶部，相对的侧壁和基部。在特征上沉积包含Si x Si x F z的层，其中“x”为0至0.2，“y”为 0.3〜0.9，“z”为0.1〜0.6。有意义的是，具有相同特征的Si层和顶部相对侧壁的上部被有效地横向凹入靠近特征是相对于靠近特征基部的相对侧壁的特征的下部。在这种蚀刻Si x SiCl 3 Z z-x元素层并蚀刻特征侧壁的上部之后，蚀刻基板使用屏蔽功能作为掩码。

7. 发明申请

US20070031762A1 Methods of patterning substrates; and templates comprising one or both of CdS and CdSe 失效
标题翻译：衬底图形化方法; 以及包含CdS和CdSe中的一种或两种的模板
公开(公告)号：US20070031762A1
公开(公告)日：2007-02-08
申请号：US11197877
申请日：2005-08-05
申请人： Krupakar Subramanian
发明人： Krupakar Subramanian
IPC分类号： G03F7/26
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00 , H01L21/3081 , H01L21/3086
摘要： The invention includes a template comprising one or both of CdS and CdSe adhered to a base in a desired pattern. The base can be any transparent or translucent material, and the desired pattern can include two or more separated segments. The template can be utilized for patterning a plurality of substrates. For instance, the substrates can be provided to have masking layers thereover, and the CdS and/or CdSe can be utilized as catalytic material to sequentially impart patterns in the masking layers. The imparting of the patterns can modify some regions of the masking layers relative to others, and either the modified or unmodified regions can be selectively removed to form patterned masks from the masking layers. Patterns from the patterned masks can then be transferred into the substrates.
摘要翻译：本发明包括一种模板，其中包含CdS和CdSe中的一种或两种以期望的图案粘附到基底上。基底可以是任何透明或半透明的材料，并且所需的图案可以包括两个或更多个分离的片段。模板可以用于图案化多个基板。例如，可以提供衬底以在其上具有掩模层，并且CdS和/或CdSe可以用作催化材料以依次赋予掩模层中的图案。赋予图案可以相对于其他图案修改掩模层的一些区域，并且可以选择性地去除修饰或未修饰的区域以从掩蔽层形成图案化掩模。然后可以将来自图案化掩模的图案转移到基底中。

8. 发明申请

US20060060796A1 Method and apparatus for plasma source ion implantation in metals and non-metals 审中-公开
标题翻译：用于等离子体源离子注入金属和非金属的方法和装置
公开(公告)号：US20060060796A1
公开(公告)日：2006-03-23
申请号：US11220184
申请日：2005-09-06
申请人： Krupakar Subramanian
发明人： Krupakar Subramanian
IPC分类号： H01J37/08
CPC分类号： H01J37/08 , H01J37/32412
摘要： Ion Implantation into surfaces of three-dimensional metallic and non-metallic targets is achieved by building a metallic mesh enclosure around the target through rapid-prototyping and then forming an ionized plasma about the target within an enclosing chamber and applying a pulse of high voltage between the wire mesh and the conductive walls of the chamber. The ions from the plasma are driven towards the wire mesh, since the mesh has finite transparency; some of the ions continue to move towards the target and are driven into the target from all sides simultaneously without the need of manipulation of the target object. Repetitive and alternating pulses of high voltages, typically 1 kV or higher, causes the ions to be implanted into the surface of the target. The plasma may be formed of a neutral gas introduced into the evacuated chamber and ionized therein with ionizing radiation so that a constant source of plasma is provided which surrounds the target object during the implantation process. Materials with new surface properties such as increased surface hardness and wear may be generated in this manner. Target object surfaces with sharp features, metals and non-metals can be treated by this technique. This technique would prove helpful in manipulating the surface properties of composites used in building aircrafts, automobiles, ships etc., metallic or non-metallic surfaces with sharp features, and the inner surfaces of tubular objects.
摘要翻译：离子注入到三维金属和非金属靶的表面中是通过快速原型建造围绕目标物的金属网壳，然后在封闭室内围绕目标物体形成离子化等离子体，并在丝网和腔室的导电壁。来自等离子体的离子被驱动到丝网，因为网具有有限的透明度; 一些离子继续朝向目标移动，同时从各个侧面被驱动到目标物中，而不需要对目标对象的操纵。高电压（通常为1kV或更高）的重复和交替脉冲使得离子被注入靶的表面。等离子体可以由引入真空室的中性气体形成并且在其中用电离辐射离子化，使得在植入过程期间提供围绕目标物体的恒定的等离子体源。可以以这种方式产生具有新表面性质的材料，例如增加的表面硬度和磨损。具有尖锐特征的目标物体表面，金属和非金属可以通过这种技术进行处理。这种技术将有助于操纵用于建造飞机，汽车，船舶等的具有尖锐特征的金属或非金属表面以及管状物体的内表面的复合材料的表面性质。

9. 发明申请

US20070046164A1 Method and apparatus to sort nanotubes 有权
标题翻译：纳米管分类方法和装置
公开(公告)号：US20070046164A1
公开(公告)日：2007-03-01
申请号：US11217095
申请日：2005-08-31
申请人： Krupakar Subramanian
发明人： Krupakar Subramanian
IPC分类号： H01J1/02
CPC分类号： H01J9/025 , B82Y10/00 , H01J2201/30469 , H01J2329/00
摘要： Methods and systems for sorting nanostructures, such as nanodot or nanotubes, are described. The sorting of the nanostructures removes remnants of the nanotube fabrication from the mixture or bundle of material. The sorting includes suspending the mixture in a plasma, which separated the nanostructures and remnant material. A motive force, such as gas flow or laser, is applied to the suspended nanostructures and remnants such that the larger material moves out of the plasma while the smaller material remains trapped in the plasma.
摘要翻译：描述了用于分选纳米结构或纳米管的方法和系统。纳米结构的分选从混合物或材料束中去除纳米管制造的残余物。排序包括将混合物悬浮在等离子体中，其分离出纳米结构和残留材料。将诸如气流或激光的动力施加到悬浮的纳米结构和残余物，使得较大的材料移出等离子体，同时较小的材料被捕获在等离子体中。

10. 发明申请

US20060275549A1 System for controlling placement of nanoparticles and methods of using same 有权
标题翻译：用于控制纳米颗粒放置的系统及其使用方法
公开(公告)号：US20060275549A1
公开(公告)日：2006-12-07
申请号：US11146248
申请日：2005-06-06
申请人： Krupakar Subramanian , Neal Rueger , Gurtej Sandhu
发明人： Krupakar Subramanian , Neal Rueger , Gurtej Sandhu
IPC分类号： B05D1/32 , H05H1/24 , C23C16/00
CPC分类号： B05B1/14 , B82Y30/00 , B82Y40/00 , C01B32/15 , H01J37/32366
摘要： The present invention is generally directed to a system for controlling placement of nanoparticles, and methods of using same. In one illustrative embodiment, the device includes a substrate and a plurality of funnels in the substrate, wherein each of the funnels comprises an inlet opening and an elongated, rectangular shaped outlet opening. In one illustrative embodiment, the method includes creating a dusty plasma comprising a plurality of carbon nanotubes, positioning a mask between the dusty plasma and a desired target for the carbon nanotubes, the mask having a plurality of openings extending therethrough, and extinguishing the dusty plasma to thereby allow at least some of the carbon nanotubes in the dusty plasma to pass through at least some of the plurality of openings in the mask and land on the target.
摘要翻译：本发明一般涉及一种用于控制纳米颗粒的放置的系统及其使用方法。在一个说明性实施例中，该装置包括衬底和衬底中的多个漏斗，其中每个漏斗包括入口开口和细长的矩形出口。在一个说明性实施例中，该方法包括产生包含多个碳纳米管的多尘等离子体，将掩模放置在尘埃等离子体和碳纳米管的期望目标之间，掩模具有延伸穿过其中的多个开口，并且熄灭灰尘等离子体从而允许灰尘等离子体中的至少一些碳纳米管穿过掩模中的多个开口中的至少一些并且落在目标上。

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