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    • 8. 发明专利
    • PLANAR SEMICONDUCTOR DEVICE
    • DE3275044D1
    • 1987-02-12
    • DE3275044
    • 1982-09-03
    • BOSCH GMBH ROBERT
    • FLOHRS PETER
    • H01L29/73H01L21/33H01L21/331H01L27/082H01L29/06H01L29/40H01L29/70H01L29/861
    • PCT No. PCT/DE82/00175 Sec. 371 Date Sep. 15, 1983 Sec. 102(e) Date Sep. 15, 1983 PCT Filed Sep. 3, 1982 PCT Pub. No. WO83/02529 PCT Pub. Date Jul. 21, 1983.A planar semiconductor structure is proposed which has a monocrystalline semiconductor chip (10) of a specific conductivity type, a first zone (11) of the opposite conductivity type introduced into the semiconductor chip (10) by diffusion from a main surface and together with the material making up the semiconductor chip (10) forming a p-n junction (12), and a passivation layer (13) covering this same main surface of the semiconductor chip (10) with the exception of contact windows. A second, annular zone (14) acting as a stop ring and having the same conductivity type as the basic material making up the semiconductor chip (10) but a higher concentration of impurities is introduced into the semiconductor chip (10) from the same main surface such that it surrounds the first zone (11). A metallizing coating acting as a cover electrode (15) is applied to the passivation layer (13), surrounding the p-n junction (12) annularly and overlapping the line of intersection of this junction with the main surface of the semiconductor chip (10). This metallizing coating extends into the region above the annular zone (14). The potential of the cover electrode (15) is adjustable such that it is between the potential of the first zone (11) and the potential of a portion of the semiconductor chip (10) located outside the first zone (11) and having a conductivity type opposite that of the first zone (11). In order to adjust the potential at the cover electrode (15), a voltage divider (16) is provided (FIG. 1).
    • 10. 发明专利
    • BR8506729A
    • 1986-09-23
    • BR8506729
    • 1985-04-16
    • BOSCH GMBH ROBERT
    • FLOHRS PETERMICHEL HARTMUT
    • H01L29/73H01L21/331H01L21/8222H01L23/528H01L27/08H01L27/082H01L29/06H01L29/08H01L29/40
    • PCT No. PCT/DE85/00118 Sec. 371 Date Aug. 21, 1985 Sec. 102(e) Date Aug. 21, 1985 PCT Filed Apr. 16, 1985 PCT Pub. No. WO85/05497 PCT Pub. Date Dec. 5, 1985.A semiconductor arrangement is suggested which is provided with a capacity transistor and a drive transistor in form of a Dralington-circuit. Thereby, the two transistors are monolithically integrated with a planar technique in a common substrate (8), which forms the two collector zones of the two transistors (T1,T2). A passivation layer (14) covers the main face of substrate (8) covering this main surface with the exception of contact windows. A cover electrode (13) is disposed above the passivation layer in the area between the collector zone and the base zone (4) of the capacity transistor (T2), whereby this passivation layer is connected with a resistor strip (2) at a distance from the base zone (4) for adjusting its potential. An additional guard strip (3) is diffused into the main surface between the resistor strip (2) and the base zone (4). In order to prevent a voltage rupture in the area of the resistor strip (2), the passivation layer is designed thinner at the area adjacent the base zone (4) than in the remaining area beneath the cover electrode (13).