专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2010147857A2 DEPENDENCE PREDICTION IN A MEMORY SYSTEM 审中-公开
标题翻译：记忆系统中的依赖性预测
公开(公告)号：WO2010147857A2
公开(公告)日：2010-12-23
申请号：PCT/US2010/038360
申请日：2010-06-11
申请人： BOARD OF REGENTS, UNIVERSITY OF TEXAS SYSTEM , BURGER, Doug , KECKLER, Stephen, W. , McDONALD, Robert , SETHUMADHAVAN, Lakshminarasimhan , ROESNER, Franziska
发明人： BURGER, Doug , KECKLER, Stephen, W. , McDONALD, Robert , SETHUMADHAVAN, Lakshminarasimhan , ROESNER, Franziska
CPC分类号： G06F9/3834 , G06F9/3838
摘要： Techniques related to dependence prediction for a memory system are generally described. Various implementations may include a predictor storage storing a value corresponding to at least one prediction type associated with at least one load operation, and a state-machine having multiple states. For example, the state-machine may determine whether to execute the load operation based upon a prediction type associated with each of the states and a corresponding precedent to the load operation for the associated prediction type. The state-machine may further determine the prediction type for a subsequent load operation based on a result of the load operation. The states of the state machine may correspond to prediction types, which may be a conservative prediction type, an aggressive prediction type, or one or more N-store prediction types, for example.
摘要翻译：通常描述与存储器系统的依赖性预测相关的技术。各种实现可以包括存储对应于与至少一个加载操作相关联的至少一个预测类型的值的预测器存储器和具有多个状态的状态机。例如，状态机可以基于与每个状态相关联的预测类型以及相关联的预测类型的加载操作的相应先例来确定是否执行加载操作。状态机可以基于加载操作的结果进一步确定后续加载操作的预测类型。状态机的状态例如可以对应于预测类型，其可以是保守预测类型，积极预测类型或一个或多个N-存储预测类型。

2. 发明申请

WO2009006607A1 DYNAMICALLY COMPOSING PROCESSOR CORES TO FORM LOGICAL PROCESSORS 审中-公开
标题翻译：将动态处理器与动态处理器动态组合
公开(公告)号：WO2009006607A1
公开(公告)日：2009-01-08
申请号：PCT/US2008/069226
申请日：2008-07-03
申请人： BOARD OF REGENTS, UNIVERSITY OF TEXAS SYSTEM , BURGER, Douglas, C. , KECKLER, Stephen, W. , MCDONALD, Robert , GRATZ, Paul , RANGANATHAN, Nitya , SETHUMADHAVAN, Lakshminarasimhan , SANKARALINGAM, Karthikeyan , NAGARAJAN, Ramadass , KIM, Changkyu , LIU, Haiming
发明人： BURGER, Douglas, C. , KECKLER, Stephen, W. , MCDONALD, Robert , GRATZ, Paul , RANGANATHAN, Nitya , SETHUMADHAVAN, Lakshminarasimhan , SANKARALINGAM, Karthikeyan , NAGARAJAN, Ramadass , KIM, Changkyu , LIU, Haiming
IPC分类号： G06F1/00
CPC分类号： G06F9/3885 , G06F9/3836 , G06F9/3897 , G06F12/0875 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： A method, system and computer program product for dynamically composing processor cores to form logical processors. Processor cores are composable in that the processor cores are dynamically allocated to form a logical processor to handle a change in the operating status. Once a change in the operating status is detected, a mechanism may be triggered to recompose one or more processor cores into a logical processor to handle the change in the operating status. An analysis may be performed as to how one or more processor cores should be recomposed to handle the change in the operating status. After the analysis, the one or more processor cores are recomposed into the logical processor to handle the change in the operating status. By dynamically allocating the processor cores to handle the change in the operating status, performance and power efficiency is improved.
摘要翻译：一种用于动态组成处理器内核以形成逻辑处理器的方法，系统和计算机程序产品。处理器核心是可组合的，因为处理器核心被动态地分配以形成逻辑处理器来处理操作状态的改变。一旦检测到操作状态的改变，则可以触发一种机制来将一个或多个处理器核重组到逻辑处理器中以处理操作状态的变化。可以执行关于如何重组一个或多个处理器核来处理操作状态的变化的分析。在分析之后，将一个或多个处理器核重新组合到逻辑处理器中以处理操作状态的改变。通过动态分配处理器核以处理运行状态的变化，提高了性能和功率效率。

3. 发明申请

WO2011034643A2 DATA MULTICASTING IN A DISTRIBUTED PROCESSOR SYSTEM 审中-公开
标题翻译：分布式处理器系统中的数据采集
公开(公告)号：WO2011034643A2
公开(公告)日：2011-03-24
申请号：PCT/US2010/038372
申请日：2010-06-11
申请人： BOARD OF REGENTS, UNIVERSITY OF TEXAS SYSTEM , BURGER, Doug , KECKLER, Stephen, W. , LI, Dong
发明人： BURGER, Doug , KECKLER, Stephen, W. , LI, Dong
CPC分类号： G06F9/30145 , G06F9/3824 , G06F9/3828 , G06F9/3885
摘要： Methods, procedures, apparatuses, computer programs, computer-accessible mediums, processing arrangements and systems generally related to data multi-casting in a distributed processor architecture are described. Various implementations may include identifying a plurality of target instructions that are configured to receive a first message from a source; providing target routing instructions to the first message for each of the target instructions including selected information commonly shared by the target instructions; and, when two of the identified target instructions are located in different directions from one another relative to a router, replicating the first message and routing the replicated messages to each of the identified target instructions in the different directions. The providing target routing instructions may further comprise the selected information utilizing a subset of bits that is commonly shared by the target instructions and being identified as a left operand, right operand or predicate operand, and may include the selection of one of a plurality of multiple-instruction subsets of the target instructions.
摘要翻译：描述了一般涉及分布式处理器架构中的数据多播的方法，程序，装置，计算机程序，计算机可访问介质，处理布置和系统。各种实现可以包括识别被配置为从源接收第一消息的多个目标指令; 为每个目标指令向第一消息提供目标路由指令，包括由目标指令共同共享的所选信息; 并且当所识别的目标指令中的两个相对于路由器彼此位于不同的方向时，复制第一消息并将复制的消息路由到不同方向上的所识别的目标指令中的每一个。提供目标路由指令还可以包括使用由目标指令共同共享并被识别为左操作数，右操作数或谓词操作数的位的子集的所选择的信息，并且可以包括选择多个多个 - 目标指令的指导子集。

4. 发明申请

WO2011031361A1 METHOD, SYSTEM AND COMPUTER-ACCESSIBLE MEDIUM FOR PROVIDING A DISTRIBUTED PREDICATE PREDICTION 审中-公开
标题翻译：用于提供分布式预测预测的方法，系统和计算机可访问介质
公开(公告)号：WO2011031361A1
公开(公告)日：2011-03-17
申请号：PCT/US2010/038350
申请日：2010-06-11
申请人： BOARD OF REGENTS, UNIVERSITY OF TEXAS SYSTEM , BURGER, Doug , KECKLER, Stephen, W. , ESMAEILZADEH, Hadi
发明人： BURGER, Doug , KECKLER, Stephen, W. , ESMAEILZADEH, Hadi
IPC分类号： G06F7/38
CPC分类号： G06F8/4451 , G06F9/3836 , G06F9/3842 , G06F9/3844
摘要： Examples of a system, method and computer accessible medium are provided to generate a predicate prediction for a distributed multi-core architecture. Using such system, method and computer accessible medium, it is possible to intelligently encode approximate predicate path information on branch instructions. Using this statically generated information, distributed predicate predictors can generate dynamic predicate histories that can facilitate an accurate prediction of high-confidence predicates, while minimizing the communication between the cores.
摘要翻译：提供系统，方法和计算机可访问介质的示例以生成分布式多核架构的谓词预测。使用这样的系统，方法和计算机可访问介质，可以智能地编码关于分支指令的近似谓词路径信息。使用这种静态生成的信息，分布式谓词预测器可以生成动态谓词历史，可以促进高信度谓词的准确预测，同时最小化内核之间的通信。

5. 发明申请

WO2010147855A1 SCALABLE BUS-BASED ON-CHIP INTERCONNECTION NETWORKS 审中-公开
标题翻译：基于总线的片上互连网络
公开(公告)号：WO2010147855A1
公开(公告)日：2010-12-23
申请号：PCT/US2010/038320
申请日：2010-06-11
申请人： BOARD OF REGENTS, UNIVERSITY OF TEXAS SYSTEM , KECKLER, Stephen, W. , GROT, Boris
发明人： KECKLER, Stephen, W. , GROT, Boris
IPC分类号： H04W40/24 , G06F13/00
CPC分类号： G06F15/7825
摘要： The present disclosure generally relates to systems for routing data across a multinodal network. Example systems include a multinodal array having a plurality of nodes and a plurality of physical communication channels connecting the nodes. At least one of the physical communication channels may be configured to route data from a first node to two or more other destination nodes of the plurality of nodes. The present disclosure also generally relates to methods for routing data across a multinodal network and computer accessible mediums having stored thereon computer executable instructions for performing techniques for routing data across a multinodal network.
摘要翻译：本公开通常涉及用于在多节点网络上路由数据的系统。示例系统包括具有多个节点的多节点阵列和连接节点的多个物理通信信道。物理通信信道中的至少一个可以被配置为将数据从第一节点路由到多个节点中的两个或更多个其他目的地节点。本公开还通常涉及用于跨越多节点网络路由数据的方法以及其上存储有用于执行跨越多节点网络路由数据的技术的计算机可执行指令的计算机可访问介质。

6. 发明申请

WO2003088048A1 NON-UNIFORM CACHE APPARATUS, SYSTEMS, AND METHODS 审中-公开
标题翻译：非均匀高速缓存设备，系统和方法
公开(公告)号：WO2003088048A1
公开(公告)日：2003-10-23
申请号：PCT/US2003/010621
申请日：2003-04-08
申请人： UNIVERSITY OF TEXAS SYSTEM , BURGER, Doug , KECKLER, Stephen, W. , KIM, Changkyu
发明人： BURGER, Doug , KECKLER, Stephen, W. , KIM, Changkyu
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0846 , G06F12/12 , G06F2212/271
摘要： An apparatus or system may comprises cache control circuitry coupled to a processor, and a plurality of independently accessible memory banks (228) coupled to the cache control circuitry. Some of the banks may have non-uniform latencies, organized into two or more spread bank sets (246). A method may include accessing data in the banks, wherein selected banks are closer to the cache control circuitry and/or processor than others, and migrating a first datum (445) to a closer bank from a further bank upon determining that the first datum is accessed more frequently than a second datum, which may be migrated to the further bank (451).
摘要翻译：装置或系统可以包括耦合到处理器的高速缓存控制电路和耦合到高速缓存控制电路的多个可独立存取的存储体（228）。一些银行可能会有不一致的延迟，组织成两个或更多的传播银行集（246）。方法可以包括访问存储体中的数据，其中所选择的存储体比其他库更靠近高速缓存控制电路和/或处理器，并且在确定第一数据是第一数据是第一数据比第二基准更频繁地访问，第二基准可以迁移到另外的银行（451）。

7. 发明申请

WO2003038645A3 A SCALABLE PROCESSING ARCHITECTURE 审中-公开
公开(公告)号：WO2003038645A3
公开(公告)日：2003-05-08
申请号：PCT/US2002/034965
申请日：2002-10-31
申请人： UNIVERSITY OF TEXAS , BURGER, Doug , KECKLER, Stephen, W. , SANKARALINGAM, Karthikeyan , NAGARAJAN, Ramadass
发明人： BURGER, Doug , KECKLER, Stephen, W. , SANKARALINGAM, Karthikeyan , NAGARAJAN, Ramadass
IPC分类号： G06F09/38
摘要： A computation node according to various embodiments of the invention includes at least one input port capable of being coupled to at least one first other 5 computation node, a first store coupled to the input port(s) to store input data, a second store to receive and store instructions, an instruction wakeup unit to match the input data to the instructions, at least one execution unit to execute the instructions, using the input data to produce output data, and at least one output port capable of being coupled to at least one second other computation node. The node may also include a router to direct the output data from the output port(s) to the second other node. A system according to various embodiments of the invention includes an external instruction sequencer to fetch a group of instructions, and one or more interconnected, preselected computational nodes. An article according to an embodiment of the invention includes a medium having instructions which are capable of causing a machine to partition a program into a plurality of groups of instructions, assign one or more of the instruction groups to a plurality of interconnected preselected computation nodes, load the instruction groups on to the nodes, and execute the instruction groups as each instruction in each group receives all necessary associated operands for execution.

8. 发明申请

WO2003038645A2 A SCALABLE PROCESSING ARCHITECTURE 审中-公开
标题翻译：可扩展的处理结构
公开(公告)号：WO2003038645A2
公开(公告)日：2003-05-08
申请号：PCT/US2002/034965
申请日：2002-10-31
申请人： UNIVERSITY OF TEXAS , BURGER, Doug , KECKLER, Stephen, W. , SANKARALINGAM, Karthikeyan , NAGARAJAN, Ramadass
发明人： BURGER, Doug , KECKLER, Stephen, W. , SANKARALINGAM, Karthikeyan , NAGARAJAN, Ramadass
IPC分类号： G06F15/76
CPC分类号： G06F15/8007 , G06F9/4494
摘要： A computation node according to various embodiments of the invention includes at least one input port capable of being coupled to at least one first other 5 computation node, a first store coupled to the input port(s) to store input data, a second store to receive and store instructions, an instruction wakeup unit to match the input data to the instructions, at least one execution unit to execute the instructions, using the input data to produce output data, and at least one output port capable of being coupled to at least one second other computation node. The node may also include a router to direct the output data from the output port(s) to the second other node. A system according to various embodiments of the invention includes an external instruction sequencer to fetch a group of instructions, and one or more interconnected, preselected computational nodes. An article according to an embodiment of the invention includes a medium having instructions which are capable of causing a machine to partition a program into a plurality of groups of instructions, assign one or more of the instruction groups to a plurality of interconnected preselected computation nodes, load the instruction groups on to the nodes, and execute the instruction groups as each instruction in each group receives all necessary associated operands for execution.
摘要翻译：根据本发明的各种实施例的计算节点包括能够耦合到至少一个第一其他计算节点的至少一个输入端口，耦合到所述输入端口以存储输入数据的第一存储器，用于接收的第二存储器并且存储指令，将输入数据与指令相匹配的指令唤醒单元，使用输入数据产生输出数据的执行指令的至少一个执行单元，以及至少能够耦合到至少一个第二个其他计算节点。节点还可以包括将输出数据从输出端口引导到第二另一个节点的路由器。根据本发明的各种实施例的系统包括用于获取一组指令的外部指令定序器以及一个或多个互连的预先选择的计算节点。根据本发明的实施例的物品包括具有能够使机器将程序分成多组指令的指令的介质，将一个或多个指令组分配给多个互连的预选计算节点，将指令组加载到节点，并执行指令组，因为每个组中的每个指令都接收所有必需的相关操作数以供执行。

9. 发明申请

WO2011159309A1 COMBINED BRANCH TARGET AND PREDICATE PREDICTION 审中-公开
标题翻译：组合分支目标和预测预测
公开(公告)号：WO2011159309A1
公开(公告)日：2011-12-22
申请号：PCT/US2010/039162
申请日：2010-06-18
申请人： THE BOARD OF REGENTS OF THE UNIVERSITY OF TEXAS SYSTEM , BURGER, Douglas, C. , KECKLER, Stephen, W.
发明人： BURGER, Douglas, C. , KECKLER, Stephen, W.
IPC分类号： G06F9/45 , G06F15/00
CPC分类号： G06F9/3806 , G06F9/30058 , G06F9/30072 , G06F9/38 , G06F9/3804 , G06F9/3836 , G06F9/45516
摘要： Embodiments provide methods, apparatus, systems, and computer readable media associated with predicting predicates and branch targets during execution of programs using combined branch target and predicate predictions. The predictions may be made using one or more prediction control flow graphs which represent predicates in instruction blocks and branches between blocks in a program. The prediction control flow graphs may be structured as trees such that each node in the graphs is associated with a predicate instruction, and each leaf associated with a branch target which jumps to another block. During execution of a block, a prediction generator may take a control point history and generate a prediction. Following the path suggested by the prediction through the tree, both predicate values and branch targets may be predicted. Other embodiments may be described and claimed.
摘要翻译：实施例提供了在使用组合分支目标和谓词预测的程序执行期间预测谓词和分支目标相关联的方法，装置，系统和计算机可读介质。可以使用表示程序中的指令块中的谓词和块之间的分支的一个或多个预测控制流程图来进行预测。预测控制流图可以被构造为树，使得图中的每个节点与谓词指令相关联，并且每个叶与跳转到另一块的分支目标相关联。在块的执行期间，预测发生器可以采取控制点历史并产生预测。按照通过树的预测建议的路径，可以预测谓词值和分支目标。可以描述和要求保护其他实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式