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1. 发明申请

WO2003038645A3 A SCALABLE PROCESSING ARCHITECTURE 审中-公开
公开(公告)号：WO2003038645A3
公开(公告)日：2003-05-08
申请号：PCT/US2002/034965
申请日：2002-10-31
申请人： UNIVERSITY OF TEXAS , BURGER, Doug , KECKLER, Stephen, W. , SANKARALINGAM, Karthikeyan , NAGARAJAN, Ramadass
发明人： BURGER, Doug , KECKLER, Stephen, W. , SANKARALINGAM, Karthikeyan , NAGARAJAN, Ramadass
IPC分类号： G06F09/38
摘要： A computation node according to various embodiments of the invention includes at least one input port capable of being coupled to at least one first other 5 computation node, a first store coupled to the input port(s) to store input data, a second store to receive and store instructions, an instruction wakeup unit to match the input data to the instructions, at least one execution unit to execute the instructions, using the input data to produce output data, and at least one output port capable of being coupled to at least one second other computation node. The node may also include a router to direct the output data from the output port(s) to the second other node. A system according to various embodiments of the invention includes an external instruction sequencer to fetch a group of instructions, and one or more interconnected, preselected computational nodes. An article according to an embodiment of the invention includes a medium having instructions which are capable of causing a machine to partition a program into a plurality of groups of instructions, assign one or more of the instruction groups to a plurality of interconnected preselected computation nodes, load the instruction groups on to the nodes, and execute the instruction groups as each instruction in each group receives all necessary associated operands for execution.

2. 发明申请

WO2003038645A2 A SCALABLE PROCESSING ARCHITECTURE 审中-公开
标题翻译：可扩展的处理结构
公开(公告)号：WO2003038645A2
公开(公告)日：2003-05-08
申请号：PCT/US2002/034965
申请日：2002-10-31
申请人： UNIVERSITY OF TEXAS , BURGER, Doug , KECKLER, Stephen, W. , SANKARALINGAM, Karthikeyan , NAGARAJAN, Ramadass
发明人： BURGER, Doug , KECKLER, Stephen, W. , SANKARALINGAM, Karthikeyan , NAGARAJAN, Ramadass
IPC分类号： G06F15/76
CPC分类号： G06F15/8007 , G06F9/4494
摘要： A computation node according to various embodiments of the invention includes at least one input port capable of being coupled to at least one first other 5 computation node, a first store coupled to the input port(s) to store input data, a second store to receive and store instructions, an instruction wakeup unit to match the input data to the instructions, at least one execution unit to execute the instructions, using the input data to produce output data, and at least one output port capable of being coupled to at least one second other computation node. The node may also include a router to direct the output data from the output port(s) to the second other node. A system according to various embodiments of the invention includes an external instruction sequencer to fetch a group of instructions, and one or more interconnected, preselected computational nodes. An article according to an embodiment of the invention includes a medium having instructions which are capable of causing a machine to partition a program into a plurality of groups of instructions, assign one or more of the instruction groups to a plurality of interconnected preselected computation nodes, load the instruction groups on to the nodes, and execute the instruction groups as each instruction in each group receives all necessary associated operands for execution.
摘要翻译：根据本发明的各种实施例的计算节点包括能够耦合到至少一个第一其他计算节点的至少一个输入端口，耦合到所述输入端口以存储输入数据的第一存储器，用于接收的第二存储器并且存储指令，将输入数据与指令相匹配的指令唤醒单元，使用输入数据产生输出数据的执行指令的至少一个执行单元，以及至少能够耦合到至少一个第二个其他计算节点。节点还可以包括将输出数据从输出端口引导到第二另一个节点的路由器。根据本发明的各种实施例的系统包括用于获取一组指令的外部指令定序器以及一个或多个互连的预先选择的计算节点。根据本发明的实施例的物品包括具有能够使机器将程序分成多组指令的指令的介质，将一个或多个指令组分配给多个互连的预选计算节点，将指令组加载到节点，并执行指令组，因为每个组中的每个指令都接收所有必需的相关操作数以供执行。

3. 发明申请

WO2009006607A1 DYNAMICALLY COMPOSING PROCESSOR CORES TO FORM LOGICAL PROCESSORS 审中-公开
标题翻译：将动态处理器与动态处理器动态组合
公开(公告)号：WO2009006607A1
公开(公告)日：2009-01-08
申请号：PCT/US2008/069226
申请日：2008-07-03
申请人： BOARD OF REGENTS, UNIVERSITY OF TEXAS SYSTEM , BURGER, Douglas, C. , KECKLER, Stephen, W. , MCDONALD, Robert , GRATZ, Paul , RANGANATHAN, Nitya , SETHUMADHAVAN, Lakshminarasimhan , SANKARALINGAM, Karthikeyan , NAGARAJAN, Ramadass , KIM, Changkyu , LIU, Haiming
发明人： BURGER, Douglas, C. , KECKLER, Stephen, W. , MCDONALD, Robert , GRATZ, Paul , RANGANATHAN, Nitya , SETHUMADHAVAN, Lakshminarasimhan , SANKARALINGAM, Karthikeyan , NAGARAJAN, Ramadass , KIM, Changkyu , LIU, Haiming
IPC分类号： G06F1/00
CPC分类号： G06F9/3885 , G06F9/3836 , G06F9/3897 , G06F12/0875 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： A method, system and computer program product for dynamically composing processor cores to form logical processors. Processor cores are composable in that the processor cores are dynamically allocated to form a logical processor to handle a change in the operating status. Once a change in the operating status is detected, a mechanism may be triggered to recompose one or more processor cores into a logical processor to handle the change in the operating status. An analysis may be performed as to how one or more processor cores should be recomposed to handle the change in the operating status. After the analysis, the one or more processor cores are recomposed into the logical processor to handle the change in the operating status. By dynamically allocating the processor cores to handle the change in the operating status, performance and power efficiency is improved.
摘要翻译：一种用于动态组成处理器内核以形成逻辑处理器的方法，系统和计算机程序产品。处理器核心是可组合的，因为处理器核心被动态地分配以形成逻辑处理器来处理操作状态的改变。一旦检测到操作状态的改变，则可以触发一种机制来将一个或多个处理器核重组到逻辑处理器中以处理操作状态的变化。可以执行关于如何重组一个或多个处理器核来处理操作状态的变化的分析。在分析之后，将一个或多个处理器核重新组合到逻辑处理器中以处理操作状态的改变。通过动态分配处理器核以处理运行状态的变化，提高了性能和功率效率。

4. 发明申请

WO2014137864A1 A METHOD, APPARATUS, SYSTEM FOR HANDLING ADDRESS CONFLICTS IN A DISTRIBUTED MEMORY FABRIC ARCHITECTURE 审中-公开
标题翻译：在分布式存储器织物架构中处理地址冲突的方法，装置，系统
公开(公告)号：WO2014137864A1
公开(公告)日：2014-09-12
申请号：PCT/US2014/019790
申请日：2014-03-03
申请人： INTEL CORPORATION , NAGARAJAN, Ramadass , MILSTREY, Robert G. , KLINGLESMITH, Michael T.
发明人： NAGARAJAN, Ramadass , MILSTREY, Robert G. , KLINGLESMITH, Michael T.
IPC分类号： G06F13/14 , G06F13/20 , G06F12/00
CPC分类号： G06F12/0815 , G06F12/02 , G06F12/08 , G06F12/0806 , G06F12/0844 , G06F2212/621
摘要： Method, apparatus and system for handling address conflicts in distributed memory fabrics. Memory access requests originating from caching agents and Input/Output (I/O) agents in a computer system are serviced concurrently through use of a distributed memory fabric architecture employing parallel pipelines while maintaining memory coherency for cachelines associated with the caching agents and enforcing memory access ordering for memory access requests originating from I/O agents.
摘要翻译：用于处理分布式存储器结构中的地址冲突的方法，装置和系统。来自计算机系统中的高速缓存代理和输入/输出（I / O）代理的存储器访问请求通过使用并行管道的分布式存储器结构架构并行地进行服务，同时保持与高速缓存代理相关联的高速缓存存储器的内存一致性并执行存储器访问订购源自I / O代理的内存访问请求。

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