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1. 发明授权

US06579657B1 Material for forming a fine pattern and method for manufacturing a semiconductor device using the same 失效
标题翻译：用于形成精细图案的材料和使用其制造半导体器件的方法
公开(公告)号：US06579657B1
公开(公告)日：2003-06-17
申请号：US09049072
申请日：1998-03-27
申请人： Takeo Ishibashi , Toshiyuki Toyoshima , Keiichi Katayama , Ayumi Minamide
发明人： Takeo Ishibashi , Toshiyuki Toyoshima , Keiichi Katayama , Ayumi Minamide
IPC分类号： G03F740
CPC分类号： H01L21/0271 , G03F7/0035 , G03F7/038 , G03F7/40 , H01L21/0273
摘要： A resist pattern, containing a material capable of generating an acid by exposure to light, is covered with a resist containing a material capable of crosslinkage in the presence of an acid. The acid is generated in the resist pattern by application of heat or by exposure to light, and a crosslinked layer is formed at the interface as a cover layer for the resist pattern, thereby causing the resist pattern to be thickened. Thus, the hole diameter of the resist pattern can be reduced, or the isolation width of a resist pattern can be reduced.
摘要翻译：含有能够通过曝光产生酸的材料的抗蚀剂图案被含有能够在酸存在下能够交联的材料的抗蚀剂覆盖。通过施加热或暴露于光而在抗蚀剂图案中产生酸，并且在界面处形成交联层作为抗蚀剂图案的覆盖层，从而使抗蚀剂图案变厚。因此，可以减小抗蚀剂图案的孔径，或者可以减小抗蚀剂图案的隔离宽度。

2. 发明授权

US06171761B2 Resist pattern forming method utilizing multiple baking and partial development steps 失效
标题翻译：利用多个烘烤和部分显影步骤的抗蚀图案形成方法
公开(公告)号：US06171761B2
公开(公告)日：2001-01-09
申请号：US09231627
申请日：1999-01-15
申请人： Ayumi Minamide , Takeo Ishibashi
发明人： Ayumi Minamide , Takeo Ishibashi
IPC分类号： G03C500
CPC分类号： G03F7/40
摘要： An improved method of forming a resist pattern permitting control of a resist profile of a chemically amplified-type resist is provided. A chemically amplified-type resist is exposed to light using a mask. The resist is then baked by PEB at a first temperature, and developed halfway. The resist is baked again at a second temperature lower than the first temperature, and then fully developed. A resist pattern is thus obtained.
摘要翻译：提供了形成允许控制化学放大型抗蚀剂的抗蚀剂轮廓的抗蚀剂图案的改进方法。使用掩模将化学放大型抗蚀剂曝光。然后将抗蚀剂在第一个温度下由PEB烘烤，并在中间显影。在低于第一温度的第二温度下再次烘烤抗蚀剂，然后充分显影。由此获得抗蚀剂图案。

3. 发明授权

US5858620A Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5858620A
公开(公告)日：1999-01-12
申请号：US785846
申请日：1997-01-24
申请人： Takeo Ishibashi , Ayumi Minamide , Toshiyuki Toyoshima , Keiichi Katayama
发明人： Takeo Ishibashi , Ayumi Minamide , Toshiyuki Toyoshima , Keiichi Katayama
IPC分类号： G03F7/00 , G03F7/40 , H01L21/027 , H01L21/311 , H01L21/3213 , G03C5/00
CPC分类号： H01L21/32139 , G03F7/0035 , G03F7/40 , H01L21/0273 , H01L21/31144 , G03F7/405
摘要： A first resist pattern, which is capable of generating an acid, is formed on a semiconductor device layer. Over the first resist pattern, a layer of a second resist, which is capable of undergoing an cross-linking reaction in the presence of an acid, is formed. Then, a cross-linked film is formed in portions of said layer of the second resist at the boundary with said first resist by action of an acid from said first resist. Thereafter, non-cross-linked portions of said second resist are removed to form a finely isolated resist pattern. The semiconductor device layer is etched, via a mask of said finely isolated resist pattern, to form a fine spaces or holes.
摘要翻译：能够产生酸的第一抗蚀剂图案形成在半导体器件层上。在第一抗蚀剂图案上，形成能够在酸存在下进行交联反应的第二抗蚀剂层。然后，通过来自所述第一抗蚀剂的酸的作用，在与所述第一抗蚀剂的边界处的所述第二抗蚀剂层的部分形成交联膜。此后，除去所述第二抗蚀剂的非交联部分以形成精细隔离的抗蚀剂图案。通过所述精细隔离的抗蚀剂图案的掩模蚀刻半导体器件层，以形成精细的空间或孔。

4. 发明授权

US5892291A Registration accuracy measurement mark 失效
标题翻译：注册精度测量标记
公开(公告)号：US5892291A
公开(公告)日：1999-04-06
申请号：US670313
申请日：1996-06-27
申请人： Koichiro Narimatsu , Shigenori Yamashita , Nobuyuki Yoshioka , Shinya Soeda , Atsushi Hachisuka , Koji Taniguchi , Yuki Miyamoto , Takayuki Saito , Ayumi Minamide
发明人： Koichiro Narimatsu , Shigenori Yamashita , Nobuyuki Yoshioka , Shinya Soeda , Atsushi Hachisuka , Koji Taniguchi , Yuki Miyamoto , Takayuki Saito , Ayumi Minamide
IPC分类号： G03F1/36 , G03F1/42 , G03F7/20 , G03F9/00 , H01L21/027 , H05K1/02 , H01L23/544
CPC分类号： G03F7/706 , G03F7/70633 , Y10T428/24802 , Y10T428/24917
摘要： The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.
摘要翻译：本发明包括形成在第一层中的第一半导体元件形成元件，通过与第一半导体元件形成元件相同的制造步骤形成的第一测量标记，形成在第一层之上的第二层中的第二半导体元件形成元件，以及在与第二半导体元件形成部件相同的制造步骤中形成的用于测量第一和第二半导体元件形成部件之间的配准精度的第二测量标记。第一测量标记具有在照射光时受到与第一半导体元件形成部件相同的像差影响的图案，并且第二测量标记具有受光照射时受到与第二半导体元件形成部件相同的像差影响的图案。因此，可以提供考虑到像差影响的配准精度测量标记。

5. 发明授权

US08563200B2 Manufacturing method of photomask, method for optical proximity correction, and manufacturing method of semiconductor device 有权
标题翻译：光掩模的制造方法，光学邻近校正方法以及半导体器件的制造方法
公开(公告)号：US08563200B2
公开(公告)日：2013-10-22
申请号：US13345367
申请日：2012-01-06
申请人： Ayumi Minamide , Akemi Moniwa , Akira Imai
发明人： Ayumi Minamide , Akemi Moniwa , Akira Imai
IPC分类号： G03F1/20
CPC分类号： H01L21/02225 , G03F1/36 , G06F17/5081 , Y10S430/143
摘要： A manufacturing method of a photomask by which a resist pattern corresponding to a pattern with designed values can be formed, a method for optical proximity correction, and a manufacturing method of a semiconductor device are provided. Proximity design features that are close to each other and estimated to violate a mask rule check are extracted. In the proximity design features, correction prohibited regions where optical proximity correction is not carried out are set based on the distance between the features obtained from the extracted proximity design features and the resolution of an exposure device. Optical proximity correction is carried out on the proximity design features with the correction prohibited regions excluded to obtain corrected proximity patterns. A predetermined mask material is patterned by carrying out electron beam lithography based on the corrected proximity pattern data.
摘要翻译：提供了可以形成对应于具有设计值的图案的抗蚀剂图案的光掩模的制造方法，用于光学邻近校正的方法和半导体器件的制造方法。提取彼此靠近并估计违反掩码规则检查的接近设计特征。在接近设计特征中，基于从提取的邻近设计特征获得的特征与曝光装置的分辨率之间的距离来设置不进行光学邻近校正的校正禁止区域。对接近设计特征进行光学邻近校正，并且排除校正禁止区域以获得校正的接近度图案。通过基于校正的接近图案数据进行电子束光刻来图案化预定的掩模材料。

6. 发明授权

US08426087B2 Photomask, manufacturing apparatus and method of semiconductor device using the same, and photomask feature layout method 有权
标题翻译：光掩模，使用其的半导体器件的制造装置和方法以及光掩模特征布局方法
公开(公告)号：US08426087B2
公开(公告)日：2013-04-23
申请号：US13187955
申请日：2011-07-21
申请人： Ayumi Minamide , Mitsuru Okuno , Akemi Moniwa , Manabu Ishibashi
发明人： Ayumi Minamide , Mitsuru Okuno , Akemi Moniwa , Manabu Ishibashi
IPC分类号： G03F1/38
CPC分类号： G03F1/36 , G03F1/32
摘要： A photomask is provided which can have a large depth of focus even if four main features are annularly arranged at random.The photomask has four annularly arranged main features based on design information of a circuit feature to be formed on a wafer, and a sub-feature is laid at an intersection point of two diagonal lines of a quadrangle formed by four vertices inside the four main features in order to increase a depth of focus of an exposure feature. Therefore, the depth of focus can be increased even if the main features are not arranged at a constant pitch.
摘要翻译：提供了一种光掩模，其即使四个主要特征是随机环形布置也可以具有大的聚焦深度。基于要形成在晶片上的电路特征的设计信息，光掩模具有四个环形布置的主要特征，并且子特征被放置在由四个主要特征内的四个顶点形成的四边形的两条对角线的交点处以增加曝光特征的焦点深度。因此，即使主要特征不以恒定的间距排列，也可以提高焦深。

7. 发明授权

US08119308B2 Photomask, apparatus for manufacturing semiconductor device having the photomask, and method of manufacturing semiconductor device using the photomask 有权
标题翻译：光掩模，具有光掩模的半导体装置的制造装置以及使用该光掩模的半导体装置的制造方法
公开(公告)号：US08119308B2
公开(公告)日：2012-02-21
申请号：US12394296
申请日：2009-02-27
申请人： Ayumi Minamide , Akemi Moniwa , Junjiro Sakai , Manabu Ishibashi
发明人： Ayumi Minamide , Akemi Moniwa , Junjiro Sakai , Manabu Ishibashi
IPC分类号： G03F1/00
CPC分类号： G03F1/36 , Y10T29/41
摘要： A photomask is disclosed which can suppress deterioration of the depth of focus even in the case where main features are arranged randomly. Sub-features are replaced by a quadrangular sub-feature located inside an external quadrangle which includes as part of its outer periphery the outermost portions of the original sub-features. The sub-feature after the replacement is preferably in a square shape and the length of one side thereof is determined in accordance with the length of the associated external quadrangle. A central position of the sub-feature after the replacement is preferably coincident with the center of the external quadrangle or the center of gravity of the region which includes the original sub-features.
摘要翻译：公开了即使在主要特征被随机排列的情况下也可以抑制焦深的劣化的光掩模。子特征由位于外部四边形内部的四边形子特征代替，其包括作为其外周边的一部分的原始子特征的最外部分。更换后的子特征优选为正方形，其一侧的长度根据相关的外部四边形的长度确定。替换之后的子特征的中心位置优选地与外部四边形的中心或包括原始子特征的区域的重心重合。

8. 发明授权

US06323560B1 Registration accuracy measurement mark, method of repairing defect of the mark, photomask having the mark, method of manufacturing the photo mask and method of exposure thereof 有权
标题翻译：注册精度测量标记，修理标记缺陷的方法，具有标记的光掩模，制造光掩模的方法及其曝光方法
公开(公告)号：US06323560B1
公开(公告)日：2001-11-27
申请号：US09492750
申请日：2000-01-27
申请人： Koichiro Narimatsu , Shigenori Yamashita , Nobuyuki Yoshioka , Shinya Soeda , Atsushi Hachisuka , Koji Taniguchi , Yuki Miyamoto , Takayuki Saito , Ayumi Minamide
发明人： Koichiro Narimatsu , Shigenori Yamashita , Nobuyuki Yoshioka , Shinya Soeda , Atsushi Hachisuka , Koji Taniguchi , Yuki Miyamoto , Takayuki Saito , Ayumi Minamide
IPC分类号： H01L2358
CPC分类号： G03F7/706 , G03F7/70633 , Y10T428/24802 , Y10T428/24917
摘要： The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.
摘要翻译：本发明包括形成在第一层中的第一半导体元件形成元件，通过与第一半导体元件形成元件相同的制造步骤形成的第一测量标记，形成在第一层之上的第二层中的第二半导体元件形成元件，以及在与第二半导体元件形成部件相同的制造步骤中形成的用于测量第一和第二半导体元件形成部件之间的配准精度的第二测量标记。第一测量标记具有在照射光时受到与第一半导体元件形成部件相同的像差影响的图案，并且第二测量标记具有受光照射时受到与第二半导体元件形成部件相同的像差影响的图案。因此，可以提供考虑到像差影响的配准精度测量标记。

9. 发明授权

US6068952A Registration accuracy measurement mark, method of repairing defect of the mark, photomask having the mark, method of manufacturing the photomask and method of exposure thereof 有权
标题翻译：注册精度测量标记，修理标记缺陷的方法，具有标记的光掩模，制造光掩模的方法及其曝光方法
公开(公告)号：US6068952A
公开(公告)日：2000-05-30
申请号：US231664
申请日：1999-01-15
申请人： Koichiro Narimatsu , Shigenori Yamashita , Nobuyuki Yoshioka , Shinya Soeda , Atsushi Hachisuka , Koji Taniguchi , Yuki Miyamoto , Takayuki Saito , Ayumi Minamide
发明人： Koichiro Narimatsu , Shigenori Yamashita , Nobuyuki Yoshioka , Shinya Soeda , Atsushi Hachisuka , Koji Taniguchi , Yuki Miyamoto , Takayuki Saito , Ayumi Minamide
IPC分类号： G03F1/36 , G03F1/42 , G03F7/20 , G03F9/00 , H01L21/027 , H05K1/02
CPC分类号： G03F7/706 , G03F7/70633 , Y10T428/24802 , Y10T428/24917
摘要： The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.
摘要翻译：本发明包括形成在第一层中的第一半导体元件形成元件，通过与第一半导体元件形成元件相同的制造步骤形成的第一测量标记，形成在第一层之上的第二层中的第二半导体元件形成元件，以及在与第二半导体元件形成部件相同的制造步骤中形成的用于测量第一和第二半导体元件形成部件之间的配准精度的第二测量标记。第一测量标记具有在照射光时受到与第一半导体元件形成部件相同的像差影响的图案，并且第二测量标记具有受光照射时受到与第二半导体元件形成部件相同的像差影响的图案。因此，可以提供考虑到像差影响的配准精度测量标记。

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