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US5462896A Method of forming a sidewall on a semiconductor element 失效
标题翻译：在半导体元件上形成侧壁的方法
公开(公告)号：US5462896A
公开(公告)日：1995-10-31
申请号：US903465
申请日：1992-06-23
申请人： Atushi Komura , Kenji Kondo , Akira Kuroyanagi
发明人： Atushi Komura , Kenji Kondo , Akira Kuroyanagi
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/336 , H01L29/78 , H01L21/465
CPC分类号： H01L29/66719 , H01L21/31116 , H01L29/66712 , H01L29/7811 , H01L29/0615 , H01L29/0638 , H01L29/1095 , H01L29/402 , H01L29/42368
摘要： A method fabricates a semiconductor device having a sidewall made from an insulation film at each side of a gate electrode portion. The method forms a polysilicon gate electrode (11a) on a gate oxide film (10) in a predetermined region on an n.sup.- epitaxial layer (2). A CVD silicon oxide film (15) having a predetermined thickness is formed over the polysilicon gate electrode material (11a) on the n.sup.- epitaxial layer (2). A magnetron enhanced reactive ion etching apparatus is used to etch the CVD silicon oxide film (15) while pouring a CHF.sub.3 gas made by coupling carbon, hydrogen, and fluorine and an N.sub.2 gas onto the etched material, such that the CVD silicon oxide film (15) is left only at each side of the polysilicon gate electrode material (11a), to form a sidewall (16). To avoid electrodes of the magnetron enhanced reactive ion etching apparatus from staining, CHF.sub.3 /He/N.sub.2 /O.sub.2 may be used for etching.
摘要翻译：一种制造半导体器件，其具有由栅电极部分的每一侧由绝缘膜制成的侧壁。该方法在n型外延层（2）上的预定区域中的栅极氧化膜（10）上形成多晶硅栅电极（11a）。在n外延层（2）上的多晶硅栅电极材料（11a）上形成具有预定厚度的CVD氧化硅膜（15）。使用磁控增强反应离子蚀刻装置来蚀刻CVD氧化硅膜（15），同时将通过将碳，氢和氟与N 2气体偶合而形成的CHF 3气体倒入到蚀刻材料上，使得CVD氧化硅膜（ 15）仅留在多晶硅栅电极材料（11a）的每一侧，以形成侧壁（16）。为了避免磁控管增强反应离子蚀刻装置的电极染色，可以使用CHF 3 / He / N 2 / O 2进行蚀刻。

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