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1. 发明授权

US5883852A Configurable SRAM for field programmable gate array 失效
标题翻译：可编程SRAM用于现场可编程门阵列
公开(公告)号：US5883852A
公开(公告)日：1999-03-16
申请号：US28956
申请日：1998-02-23
申请人： Atul V. Ghia , Paul Takao Sasaki
发明人： Atul V. Ghia , Paul Takao Sasaki
IPC分类号： G11C7/10 , G11C8/16 , G11C11/417 , G11C11/419 , H03K19/177 , G11C8/00 , G11C16/04
CPC分类号： H03K19/1776 , G11C11/417 , G11C11/419 , G11C7/1006 , G11C8/16
摘要： A configurable SRAM for a field programmable gate array. Two memory arrays each have a data input, a data output, a write enable input and port A and B address inputs. First and second address buses are selectively coupled to the port A and port B address inputs through multiplexers such that different configurations can be achieved. The multiplexers are controlled by a dual port/single port steering signal and a x1/x2 steering signal such that the following configurations can be achieved: 32 x1 dual port; 32 x1 single port and 16 x2 single port. In dual port configurations, simultaneous read and write operations to different cells can occur. In x2 configuration, each array is operated as an independent memory with its own address input, its own data output and its own data input. In x1 single port configuration, one data input line and one data output line and one address bus are shared between the two arrays, and an extra address bit is used to steer the write enable signals and the output multiplexer circuitry such the write enable signal reaches the proper array and the data output from the array being read reaches the shared output line.
摘要翻译：用于现场可编程门阵列的可配置SRAM。两个存储器阵列各自具有数据输入，数据输出，写使能输入和端口A和B地址输入。第一和第二地址总线通过复用器选择性地耦合到端口A和端口B的地址输入，使得可以实现不同的配置。多路复用器由双端口/单端口转向信号和x1 / x2转向信号控制，从而可以实现以下配置：32 x1双端口; 32 x1单端口和16 x2单端口。在双端口配置中，可能会发生对不同单元的同时读和写操作。在x2配置中，每个阵列都作为具有自己的地址输入，自己的数据输出和自己的数据输入的独立存储器运行。在x1单端口配置中，两个阵列之间共享一个数据输入线和一个数据输出线和一个地址总线，另外一个额外的地址位用于引导写使能信号和输出多路复用器电路，使写使能信号达到正确的数组和正在读取的阵列的数据输出到达共享输出行。

2. 发明授权

US6130550A Scaleable padframe interface circuit for FPGA yielding improved routability and faster chip layout 失效
标题翻译：用于FPGA的可扩展的焊盘接口电路可提高可布线性和更快的芯片布局
公开(公告)号：US6130550A
公开(公告)日：2000-10-10
申请号：US978451
申请日：1997-11-25
申请人： Arch Zaliznyak , Suresh Manohar Menon , Paul Takao Sasaki
发明人： Arch Zaliznyak , Suresh Manohar Menon , Paul Takao Sasaki
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17744
摘要： An interface circuit for use in the layout of padframe interface circuits for field programmable gate arrays having a plurality of I/O cells each of which may be programmed as an input or an output (or both) and a programmable connection matrix which provide programmable pathways between the data output signals generated by the core array of logic blocks and I/O cells programmed as outputs and provide programmable pathways between I/O cells programmed as inputs and data input conductors going into the core array. The interface circuits are all substantially identical in structure, and each includes a sufficient number of power and ground connections to supply adequate current to the number of I/O cells the interface has. Each interface circuit also includes at least one and preferably two open spaces into which conductive paths may be laid out to carry power to the core array or carry dedicated signals to circuits other than the core which also reside on the integrated circuit. Because of the substantially identical structure of each interface and the preservation of ratios between I/O cells, power and ground connections and open slots, larger or smaller core arrays may be accommodated by cutting and pasting additional interface circuits into the layout thereby substantially decreasing design, placement and layout time and time to market for introduction of new FPGAs in a family with larger core arrays. The regular repeatable structure of RIU's simplifies software development for products within the family and as such contributes to faster "time to market".
摘要翻译：一种用于现场可编程门阵列的焊盘接口电路布局的接口电路，其具有多个I / O单元，每个I / O单元可被编程为输入或输出（或两者）和可编程连接矩阵，其提供可编程通道在由逻辑块的核心阵列和被编程为输出的I / O单元产生的数据输出信号之间，并且在被编程为输入的I / O单元和进入核心阵列的数据输入导体之间提供可编程通道。接口电路的结构基本相同，并且每个接口电路都包括足够数量的电源和接地连接，以向接口所具有的I / O单元的数量提供足够的电流。每个接口电路还包括至少一个并且优选两个开放空间，导电路径可布置在该开放空间中，以将功率传递到核心阵列，或将专用信号传送到也位于集成电路上的核心以外的电路。由于每个接口的结构基本相同，并且保持了I / O单元，电源和接地连接以及开放槽之间的比率，因此可以通过将附加的接口电路切割并粘贴到布局中来适应更大或更小的磁芯阵列，从而大大减少设计，放置和布局时间和上市时间，以便在具有较大核心阵列的家族中引入新的FPGA。 RIU的常规可重复结构简化了家庭产品的软件开发，因此有助于加快“上市时间”。

3. 发明授权

US06002268A FPGA with conductors segmented by active repeaters 失效
标题翻译：具有由有源中继器分段的导体的FPGA
公开(公告)号：US06002268A
公开(公告)日：1999-12-14
申请号：US978691
申请日：1997-11-26
申请人： Paul Takao Sasaki , Madhukar Vora , Burnell G West
发明人： Paul Takao Sasaki , Madhukar Vora , Burnell G West
IPC分类号： H03K17/62 , H03K19/0175 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1778 , H03K17/6257 , H03K17/6264 , H03K17/6285 , H03K17/6292 , H03K19/01759 , H03K19/1737 , H03K19/17704
摘要： An interface circuit for use in the layout of padframe interface circuits for field programmable gate arrays having a plurality of I/O cells each of which may be programmed as an input or an output (or both) and a programmable connection matrix which provide programmable pathways between the data output signals generated by the core array of logic blocks and I/O cells programmed as outputs and provide programmable pathways between I/O cells programmed as inputs and data input conductors going into the core array. The interface circuits are all substantially identical in structure, and each includes a sufficient number of power and ground connections to supply adequate current to the number of I/O cells the interface has. Each interface circuit also includes at least one and preferably two open spaces into which conductive paths may be laid out to carry power to the core array or carry dedicated signals to circuits other than the core which also reside on the integrated circuit. Because of the substantially identical structure of each interface and the preservation of ratios between I/O cells, power and ground connections and open slots, larger or smaller core arrays may be accommodated by cutting and pasting additional interface circuits into the layout thereby substantially decreasing design, placement and layout time and time to market for introduction of new FPGAs in a family with larger core arrays. The regular repeatable structure of RIU's simplifies software development for products within the family and as such contributes to faster "time to market".
摘要翻译：一种用于现场可编程门阵列的焊盘接口电路布局的接口电路，其具有多个I / O单元，每个I / O单元可被编程为输入或输出（或两者）和可编程连接矩阵，其提供可编程通道在由逻辑块的核心阵列和被编程为输出的I / O单元产生的数据输出信号之间，并且在被编程为输入的I / O单元和进入核心阵列的数据输入导体之间提供可编程通道。接口电路的结构基本相同，并且每个接口电路都包括足够数量的电源和接地连接，以向接口所具有的I / O单元的数量提供足够的电流。每个接口电路还包括至少一个并且优选两个开放空间，导电路径可布置在该开放空间中，以将功率传递到核心阵列，或将专用信号传送到也位于集成电路上的核心以外的电路。由于每个接口的结构基本相同，并且保持了I / O单元，电源和接地连接以及开放槽之间的比率，因此可以通过将附加的接口电路切割并粘贴到布局中来适应更大或更小的磁芯阵列，从而大大减少设计，放置和布局时间和上市时间，以便在具有较大核心阵列的家族中引入新的FPGA。 RIU的常规可重复结构简化了家庭产品的软件开发，因此有助于加快“上市时间”。

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