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    • 2. 发明授权
    • Low jitter clock for a physical media access sublayer on a field programmable gate array
    • 用于现场可编程门阵列上的物理介质访问子层的低抖动时钟
    • US06911842B1
    • 2005-06-28
    • US10090239
    • 2002-03-01
    • Atul V. GhiaVasisht M. VadiAdebabay M. BekelePhilip D. CostelloHare K. Verma
    • Atul V. GhiaVasisht M. VadiAdebabay M. BekelePhilip D. CostelloHare K. Verma
    • G06F1/04G06F1/10H03K17/693H03K19/173H03K19/77
    • G06F1/10
    • A programmable logic device (PLD) is provided that supports multi-gigabit transceivers (MGTs). The PLD includes one or more pairs of shared clock pads for receiving one or more high-quality differential clock signals. Dedicated clock traces couple each pair of shared clock pads to one or more MGTs on the PLD. Each MGT includes a clock multiplexer circuit, which allows one of the high-quality differential clock signals to be routed as a reference clock signal for the MGT. The clock multiplexer circuits are designed such that no significant jitter is added to the high-quality clock signals. The clock multiplexer circuits can also route general-purpose clock signals received by the PLD as lower quality reference clock signals for the MGTs. The reference clock signal routed by the clock multiplexer circuit can be stepped down to provide a reference clock for a physical coding sublayer of the MGT.
    • 提供了支持多千兆位收发器(MGT)的可编程逻辑器件(PLD)。 PLD包括用于接收一个或多个高质量差分时钟信号的一对或多对共享时钟焊盘。 专用时钟跟踪将每对共享时钟接口耦合到PLD上的一个或多个MGT。 每个MGT包括时钟多路复用器电路,其允许将高质量差分时钟信号中的一个作为MGT的参考时钟信号进行路由。 时钟多路复用器电路被设计成使得高质量时钟信号不会增加显着的抖动。 时钟多路复用器电路还可以将由PLD接收的通用时钟信号作为MGT的较低质量参考时钟信号。 可以降低由时钟多路复用器电路路由的参考时钟信号,为MGT的物理编码子层提供参考时钟。