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1. 发明授权

US6057220A Titanium polycide stabilization with a porous barrier 失效
标题翻译：具有多孔屏障的多晶硅化钛稳定剂
公开(公告)号：US6057220A
公开(公告)日：2000-05-02
申请号：US936029
申请日：1997-09-23
申请人： Atul C. Ajmera , Christine Dehm , Anthony G. Domenicucci , George G. Gifford , Stephen K. Loh , Christopher Parks , Viraj Y. Sardesai
发明人： Atul C. Ajmera , Christine Dehm , Anthony G. Domenicucci , George G. Gifford , Stephen K. Loh , Christopher Parks , Viraj Y. Sardesai
IPC分类号： H01L21/28 , H01L29/49 , H01L21/44 , H01L21/425
CPC分类号： H01L21/28061 , H01L29/4933
摘要： A "porous barrier" is formed without formation of a discrete barrier layer by enriching grain boundaries of a body of polysilicon with nitrogen to inhibit thermal mobility of silicon species therealong. In a polycide gate/interconnect structure, the reduced mobility of silicon suppresses agglomeration of silicon in a metal silicide layer formed thereon. Since silicon agglomeration is a precursor of a polycide inversion phenomenon, polycide inversion which can pierce an underlying oxide and cause device failure is effectively avoided. The increased thermal stability of polycide structures and other structures including a body of polysilicon thus increases the heat budget that can be withstood by the structure and increases the manufacturing process window imposed by the presence of polysilicon which can be exploited in other processes such as annealing to develop a low resistance phase of refractory metal silicide included in the polycide structure, drive-in annealing for formation of source/drain regions of field effect transistors and the like.
摘要翻译：通过用氮富集多晶硅体的晶界而形成不形成离散阻挡层的“多孔阻挡层”，以抑制硅物质的热迁移率。在多晶硅栅极/互连结构中，硅的迁移率降低抑制了在其上形成的金属硅化物层中的硅的聚集。由于硅团聚是多杀线反转现象的前体，因此有效地避免了可能刺穿潜在氧化物并导致器件故障的多硅化物反转。因此，多晶硅结构和包括多晶硅体在内的其他结构的热稳定性增加，因此增加了可被该结构承受的热量预算，并且增加了存在多晶硅所产生的制造工艺窗口，这可以在其它工艺中被利用，例如退火开发包括在多晶硅结构中的难熔金属硅化物的低电阻相，用于形成场效应晶体管的源极/漏极区域的驱动退火等。

2. 发明授权

US06342131B1 Method of depositing a multilayer thin film by means of magnetron sputtering which controls the magnetic field 失效
标题翻译：通过控制磁场的磁控溅射沉积多层薄膜的方法
公开(公告)号：US06342131B1
公开(公告)日：2002-01-29
申请号：US09061980
申请日：1998-04-17
申请人： Viraj Y. Sardesai , Tomio Y. Katata , Christopher Parks , John Benedict
发明人： Viraj Y. Sardesai , Tomio Y. Katata , Christopher Parks , John Benedict
IPC分类号： C23C1434
CPC分类号： C23C14/35
摘要： A thin film deposition method comprises the steps of preparing a magnetron sputtering system having a magnetic field generation unit for changing a magnetic field, mounting, as a target, a composite material on a cathode of the magnetron sputtering system, providing a to-be-processed substrate on an anode of the magnetron sputtering system, evacuating a chamber of the magnetron sputtering system and thereafter filling the chamber with inert gas, and applying, onto the cathode, one of DC power and RF power and, at the same time, an alternating magnetic field from a lower portion of the target, thereby controlling a cycle and intensity of the alternating magnetic field to change a ratio of the not less than two components of the thin film in a film thickness direction of the thin film.
摘要翻译：薄膜沉积方法包括以下步骤：制备具有用于改变磁场的磁场产生单元的磁控溅射系统，将复合材料安装在磁控溅射系统的阴极上作为目标，在磁控溅射系统的阳极上处理的衬底，抽空磁控溅射系统的腔室，然后用惰性气体填充室，并将阴极施加到直流电源和RF功率中的一个，同时，从目标的下部交变磁场，从而控制交变磁场的周期和强度，以改变薄膜的薄膜厚度方向上不少于两个分量的比例。

3. 发明授权

US08039888B2 Conductive spacers for semiconductor devices and methods of forming 有权
标题翻译：用于半导体器件的导电间隔件及其形成方法
公开(公告)号：US08039888B2
公开(公告)日：2011-10-18
申请号：US11848597
申请日：2007-08-31
申请人： Gary Bela Bronner , David Michael Fried , Jeffrey Peter Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Y. Sardesai
发明人： Gary Bela Bronner , David Michael Fried , Jeffrey Peter Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Y. Sardesai
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L21/26586 , H01L21/28518 , H01L21/76895 , H01L21/823468 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.
摘要翻译：一种在半导体器件上形成导电间隔物的方法。该方法包括在半导体器件上沉积多晶硅层，在半导体器件的晶体管区域的第一侧上选择性地将多晶硅层中的掺杂剂离子注入以限定导电间隔区，以及除去导电间隔区之外的多晶硅层。任选地，可以在导电间隔物区域上进行硅化处理，使得导电间隔物由金属硅化物构成。

4. 发明授权

US06497784B1 Semiconductor wafer edge bead removal method and tool 失效
标题翻译：半导体晶圆边缘除珠方法及工具
公开(公告)号：US06497784B1
公开(公告)日：2002-12-24
申请号：US09441862
申请日：1999-11-17
申请人： Bradley P. Jones , Viraj Y. Sardesai
发明人： Bradley P. Jones , Viraj Y. Sardesai
IPC分类号： H01L2100
CPC分类号： H01L21/6708 , H01L21/31053
摘要： A method for planarizing a dielectric layer on a semiconductor wafer is provided. In one aspect, the wafer is coated with a resist and the resist selectively removed forming an uncoated peripheral portion of the wafer. The partially coated wafer is then exposed to an etchant such as RIE to etch the dielectric material not covered by the resist and forming a profiled dielectric layer having a thinner peripheral dielectric portion and a remaining thicker original dielectric central portion. The profiled wafer is then planarized using CMP. The dielectric layer is typically SiO2, PSG, BSP, or BPSG. In another method and apparatus of the invention, a dielectric coated wafer is secured to a rotating turntable and a liquid etchant sprayed at the periphery of the wafer from a distribution conduit to etch and remove dielectric from a circumferential edge of the wafer forming a profiled dielectric layer as above which is then planarized by CMP. In another aspect of the invention, a CMP polished semiconductor wafer having an edge bead is planarized by polishing only the edge bead of the dielectric layer using a special polishing tool or a CMP apparatus to remove the edge bead from the dielectric layer. Planarized semiconductor wafers made using the method and apparatus of the invention are also provided.
摘要翻译：提供了一种用于平坦化半导体晶片上的电介质层的方法。在一个方面，晶片被涂覆有抗蚀剂，并且抗蚀剂被选择性地去除，形成晶片的未涂覆的周边部分。然后将部分涂覆的晶片暴露于诸如RIE的蚀刻剂以蚀刻未被抗蚀剂覆盖的介电材料，并形成具有更薄的外围电介质部分和剩余较厚的原始介电中心部分的异型电介质层。然后使用CMP对异型晶片进行平面化。电介质层通常是SiO 2，PSG，BSP或BPSG。在本发明的另一种方法和装置中，将电介质涂覆的晶片固定到旋转转盘和从分配导管在晶片周边喷射的液体蚀刻剂，以从晶圆的周边边缘蚀刻并去除电介质，从而形成异型电介质层，然后通过CMP平坦化。在本发明的另一方面，通过使用特殊的抛光工具或CMP装置仅抛光电介质层的边缘珠来平坦化具有边缘珠的CMP抛光的半导体晶片，以从电介质层去除边缘珠。还提供了使用本发明的方法和装置制造的平面化的半导体晶片。

5. 发明授权

US08853700B2 Cross-coupling of gate conductor line and active region in semiconductor devices 有权
标题翻译：半导体器件中栅极导线与有源区的交叉耦合
公开(公告)号：US08853700B2
公开(公告)日：2014-10-07
申请号：US13207102
申请日：2011-08-10
申请人： Viraj Y. Sardesai , Robert C. Wong
发明人： Viraj Y. Sardesai , Robert C. Wong
IPC分类号： H01L29/10 , H01L27/092 , H01L21/768 , H01L27/11 , H01L27/02 , H01L29/66 , H01L29/51
CPC分类号： H01L27/1104 , H01L21/76895 , H01L27/0211 , H01L27/092 , H01L29/517 , H01L29/66545 , Y10S257/903 , Y10S257/904
摘要： Cross-coupling between a gate conductor and an active region of a semiconductor substrate is provided by forming a gate dielectric layer on the semiconductor substrate and lithographically patterning the gate dielectric layer to form opening therein over a portion of the active region at which electrical contact with the gate conductor is desired. After implanting electrical dopants, a gate conductor layer is deposited and patterned. A remaining portion of the gate conductor layer includes an integral conductor structure, which includes a first portion overlying a gate dielectric over an active region and a second portion contacting the semiconductor material of the same active region or a different active region. The gate dielectric layer can be deposited within gate cavities in planarization dielectric material layer in a replacement gate scheme, or can be deposited on planar surfaces of active regions and/or shallow trench isolation structures in a gate first processing scheme.
摘要翻译：通过在半导体衬底上形成栅极电介质层并在栅极电介质层上进行光刻图案以形成开口，在有源区域的一部分上与电极接触需要栅极导体。在注入电掺杂物之后，沉积并图案化栅极导体层。栅极导体层的剩余部分包括整体导体结构，其包括覆盖有源区上的栅极电介质的第一部分和接触相同有源区或不同有源区的半导体材料的第二部分。栅极电介质层可以以替代栅极方案沉积在平坦化介电材料层的栅极腔内，或者可以在栅极第一处理方案中沉积在有源区和/或浅沟槽隔离结构的平面表面上。

6. 发明申请

US20130037864A1 CROSS-COUPLING OF GATE CONDUCTOR LINE AND ACTIVE REGION IN SEMICONDUCTOR DEVICES 有权
标题翻译：栅极导体线和半导体器件中的主动区域的交叉耦合
公开(公告)号：US20130037864A1
公开(公告)日：2013-02-14
申请号：US13207102
申请日：2011-08-10
申请人： Viraj Y. Sardesai , Robert C. Wong
发明人： Viraj Y. Sardesai , Robert C. Wong
IPC分类号： H01L27/085 , H01L21/28
CPC分类号： H01L27/1104 , H01L21/76895 , H01L27/0211 , H01L27/092 , H01L29/517 , H01L29/66545 , Y10S257/903 , Y10S257/904
摘要： Cross-coupling between a gate conductor and an active region of a semiconductor substrate is provided by forming a gate dielectric layer on the semiconductor substrate and lithographically patterning the gate dielectric layer to form opening therein over a portion of the active region at which electrical contact with the gate conductor is desired. After implanting electrical dopants, a gate conductor layer is deposited and patterned. A remaining portion of the gate conductor layer includes an integral conductor structure, which includes a first portion overlying a gate dielectric over an active region and a second portion contacting the semiconductor material of the same active region or a different active region. The gate dielectric layer can be deposited within gate cavities in planarization dielectric material layer in a replacement gate scheme, or can be deposited on planar surfaces of active regions and/or shallow trench isolation structures in a gate first processing scheme.
摘要翻译：通过在半导体衬底上形成栅极电介质层并在栅极电介质层上进行光刻图案以形成开口，在有源区域的一部分上与电极接触需要栅极导体。在注入电掺杂物之后，沉积并图案化栅极导体层。栅极导体层的剩余部分包括整体导体结构，其包括覆盖有源区上的栅极电介质的第一部分和接触相同有源区或不同有源区的半导体材料的第二部分。栅极电介质层可以以替代栅极方案沉积在平坦化介电材料层的栅极腔内，或者可以在栅极第一处理方案中沉积在有源区和/或浅沟槽隔离结构的平面表面上。

7. 发明申请

US20130020705A1 METHOD TO FORM UNIFORM SILICIDE BY SELECTIVE IMPLANTATION 有权
标题翻译：通过选择性植入形成均匀硅酮的方法
公开(公告)号：US20130020705A1
公开(公告)日：2013-01-24
申请号：US13186519
申请日：2011-07-20
申请人： Emre Alptekin , Viraj Y. Sardesai , Cung D. Tran , Bin Yang
发明人： Emre Alptekin , Viraj Y. Sardesai , Cung D. Tran , Bin Yang
IPC分类号： H01L21/28 , H01L23/50
CPC分类号： H01L23/485 , H01L21/26506 , H01L21/26513 , H01L21/26566 , H01L21/2658 , H01L21/26586 , H01L21/28518 , H01L21/76814 , H01L2924/0002 , H01L2924/00
摘要： Methods form an integrated circuit structure by forming at least a portion of a plurality of devices within and/or on a substrate and patterning trenches in an inter-layer dielectric layer on the substrate adjacent the devices. The patterning forms relatively narrow trenches and relatively wide trenches. The methods then perform an angled implant of a compensating material into the trenches. The angle of the angled implant implants a greater concentration of the compensating material in the regions of the substrate at the bottom of the wider trenches relative to an amount of compensating material implanted in the regions of the substrate at the bottom of the narrower trenches. The methods then deposit a metallic material within the trenches and heat the metallic material to form silicide from the metallic material.
摘要翻译：方法通过在衬底内和/或衬底上形成多个器件的至少一部分形成集成电路结构，并且在邻近器件的衬底上的层间电介质层中图案化沟槽。图案形成相对较窄的沟槽和较宽的沟槽。然后，所述方法对沟槽进行补偿材料的成角度注入。成角度的植入物的角度相对于在较窄沟槽的底部注入衬底的区域中的补偿材料的量，在较宽沟槽底部的衬底区域中植入更大浓度的补偿材料。然后，该方法将金属材料沉积在沟槽内，并加热金属材料以从金属材料形成硅化物。

8. 发明授权

US06268299B1 Variable stoichiometry silicon nitride barrier films for tunable etch selectivity and enhanced hyrogen permeability 有权
标题翻译：用于可调蚀刻选择性和增强的透氢性的可变化学计量氮化硅阻挡膜
公开(公告)号：US06268299B1
公开(公告)日：2001-07-31
申请号：US09668988
申请日：2000-09-25
申请人： Rajarao Jammy , Johnathan E. Faltermeier , Keitaro Imai , Ryota Katsumata , Jean-Marc Rousseau , Viraj Y. Sardesai , Joseph F. Shepard, Jr.
发明人： Rajarao Jammy , Johnathan E. Faltermeier , Keitaro Imai , Ryota Katsumata , Jean-Marc Rousseau , Viraj Y. Sardesai , Joseph F. Shepard, Jr.
IPC分类号： H01L21318
CPC分类号： C23C14/0652 , H01L21/3185
摘要： A low-temperature process for forming a highly conformal barrier film during integrated circuit manufacture by low pressure chemical vapor deposition (LPCVD). The process includes the following steps. First, the process provides ammonia and a silicon-containing gas selected from the group consisting of silane, dichlorosilane, bistertiarybutylaminosilanc, hexachlorodisilane, and mixtures of those compositions. The ratio of the volume of ammonia to the volume of the silicon-containing gas is adjusted to yield silicon concentrations greater than 43 atomic percent in the resultant film. The process applies a deposition temperature of 550° C. to 720° C. The ammonia and the silicon-containing gas are reacted at the deposition temperature to form a silicon-rich nitride film less than 200 Å thick. Finally, the silicon nitride film is deposited by low pressure chemical vapor deposition.
摘要翻译：在低压化学气相沉积（LPCVD）的集成电路制造过程中形成高保形阻挡膜的低温工艺。该过程包括以下步骤。首先，该方法提供氨和含硅气体，其选自硅烷，二氯硅烷，二丁基氨基硅烷，六氯二硅烷，以及这些组合物的混合物。调节氨体积与含硅气体体积的比例，得到所得膜中硅浓度大于43原子百分比。该方法将沉积温度为550℃至720℃。氨和含硅气体在沉积温度下反应，形成厚度小于200埃的富硅氮化物膜。最后，通过低压化学气相沉积沉积氮化硅膜。

9. 发明授权

US08492275B2 Method to form uniform silicide by selective implantation 有权
标题翻译：通过选择性植入形成均匀硅化物的方法
公开(公告)号：US08492275B2
公开(公告)日：2013-07-23
申请号：US13186519
申请日：2011-07-20
申请人： Emre Alptekin , Viraj Y. Sardesai , Cung D. Tran , Bin Yang
发明人： Emre Alptekin , Viraj Y. Sardesai , Cung D. Tran , Bin Yang
IPC分类号： H01L21/44
CPC分类号： H01L23/485 , H01L21/26506 , H01L21/26513 , H01L21/26566 , H01L21/2658 , H01L21/26586 , H01L21/28518 , H01L21/76814 , H01L2924/0002 , H01L2924/00
摘要： Methods form an integrated circuit structure by forming at least a portion of a plurality of devices within and/or on a substrate and patterning trenches in an inter-layer dielectric layer on the substrate adjacent the devices. The patterning forms relatively narrow trenches and relatively wide trenches. The methods then perform an angled implant of a compensating material into the trenches. The angle of the angled implant implants a greater concentration of the compensating material in the regions of the substrate at the bottom of the wider trenches relative to an amount of compensating material implanted in the regions of the substrate at the bottom of the narrower trenches. The methods then deposit a metallic material within the trenches and heat the metallic material to form silicide from the metallic material.
摘要翻译：方法通过在衬底内和/或衬底上形成多个器件的至少一部分形成集成电路结构，并且在邻近器件的衬底上的层间电介质层中图案化沟槽。图案形成相对较窄的沟槽和较宽的沟槽。然后，所述方法对沟槽进行补偿材料的成角度注入。成角度的植入物的角度相对于在较窄沟槽的底部注入衬底的区域中的补偿材料的量，在较宽沟槽底部的衬底区域中植入更大浓度的补偿材料。然后，该方法将金属材料沉积在沟槽内，并加热金属材料以从金属材料形成硅化物。

10. 发明申请

US20090029549A1 METHOD OF SILICIDE FORMATION FOR NANO STRUCTURES 审中-公开
标题翻译：纳米结构硅酸盐形成方法
公开(公告)号：US20090029549A1
公开(公告)日：2009-01-29
申请号：US11781599
申请日：2007-07-23
申请人： Oh-Jung Kwon , Robert J. Purtell , Viraj Y. Sardesai
发明人： Oh-Jung Kwon , Robert J. Purtell , Viraj Y. Sardesai
IPC分类号： H01L21/44
CPC分类号： H01L21/28518
摘要： A method forms a first layer over a second layer that comprises silicon. A mask is formed and patterned over the insulator layer. Then, a heavy inert gas such as Xenon (Xe) is implanted through the openings in the mask, through the insulator layer, and into the regions of the silicon layer that are below the opening in the mask. The portions of the insulator layer that are below the openings in the mask are etched away and the mask is removed. A metal or metal alloy layer is formed over the first layer and the exposed regions of the second layer. At least the second layer is heated in a silicide process such that the metal and the exposed regions of the second layer combine to form silicide regions. After this, any remaining metal material can be removed to remove to leave the silicide regions adjacent non-silicide regions of the second layer.
摘要翻译：一种方法在包含硅的第二层上形成第一层。在绝缘体层上形成并图案化掩模。然后，将诸如氙（Xe）的重惰性气体通过掩模中的开口通过绝缘体层注入掩模中开口下方的硅层的区域中。蚀刻绝缘体层中位于掩模中的开口下方的部分，并且去除掩模。金属或金属合金层形成在第一层和第二层的暴露区域之上。至少第二层在硅化物工艺中加热，使得金属和第二层的暴露区域结合形成硅化物区域。此后，可以去除任何剩余的金属材料以除去以留下与第二层的非硅化物区域相邻的硅化物区域。

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