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1. 发明授权

US08134209B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08134209B2
公开(公告)日：2012-03-13
申请号：US12640658
申请日：2009-12-17
申请人： Atsushi Yagishita , Makoto Fujiwara , Hirohisa Kawasaki , Mariko Takayanagi
发明人： Atsushi Yagishita , Makoto Fujiwara , Hirohisa Kawasaki , Mariko Takayanagi
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L21/823431 , H01L27/0886 , H01L29/66795
摘要： Multi-gate metal oxide silicon transistors and methods of making multi-gate metal oxide silicon transistors are provided. The multi-gate metal oxide silicon transistor contains a bulk silicon substrate containing one or more convex portions between shallow trench regions; one or more dielectric portions over the convex portions; one or more silicon fins over the dielectric portions; a shallow trench isolation layer in the shallow trench isolation regions; and a gate electrode. The upper surface of the shallow trench isolation layer can be located below the upper surface of the convex portion, or the upper surface of the shallow trench isolation layer can be located between the lower surface and the upper surface of first dielectric layer. The multi-gate metal oxide silicon transistor can contain second spacers adjacent to side surfaces of the convex portions in a source/drain region.
摘要翻译：提供多栅极金属氧化物硅晶体管和制造多栅极金属氧化物硅晶体管的方法。多栅极金属氧化物硅晶体管包含在浅沟槽区域之间包含一个或多个凸部的体硅衬底; 一个或多个在凸部上的电介质部分; 电介质部分上的一个或多个硅散热片; 在浅沟槽隔离区域的浅沟槽隔离层; 和栅电极。浅沟槽隔离层的上表面可以位于凸部的上表面下方，或者浅沟槽隔离层的上表面可以位于第一介电层的下表面和上表面之间。多栅极金属氧化物硅晶体管可以包含与源极/漏极区域中的凸部的侧表面相邻的第二间隔物。

2. 发明申请

US20110147839A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110147839A1
公开(公告)日：2011-06-23
申请号：US12640658
申请日：2009-12-17
申请人： Atsushi Yagishita , Makoto Fujiwara , Hirohisa Kawasaki , Mariko Takayanagi
发明人： Atsushi Yagishita , Makoto Fujiwara , Hirohisa Kawasaki , Mariko Takayanagi
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/785 , H01L21/823431 , H01L27/0886 , H01L29/66795
摘要： Multi-gate metal oxide silicon transistors and methods of making multi-gate metal oxide silicon transistors are provided. The multi-gate metal oxide silicon transistor contains a bulk silicon substrate containing one or more convex portions between shallow trench regions; one or more dielectric portions over the convex portions; one or more silicon fins over the dielectric portions; a shallow trench isolation layer in the shallow trench isolation regions; and a gate electrode. The upper surface of the shallow trench isolation layer can be located below the upper surface of the convex portion, or the upper surface of the shallow trench isolation layer can be located between the lower surface and the upper surface of first dielectric layer. The multi-gate metal oxide silicon transistor can contain second spacers adjacent to side surfaces of the convex portions in a source/drain region.
摘要翻译：提供多栅极金属氧化物硅晶体管和制造多栅极金属氧化物硅晶体管的方法。多栅极金属氧化物硅晶体管包含在浅沟槽区域之间包含一个或多个凸部的体硅衬底; 一个或多个在凸部上的电介质部分; 电介质部分上的一个或多个硅散热片; 在浅沟槽隔离区域的浅沟槽隔离层; 和栅电极。浅沟槽隔离层的上表面可以位于凸部的上表面下方，或者浅沟槽隔离层的上表面可以位于第一介电层的下表面和上表面之间。多栅极金属氧化物硅晶体管可以包含与源极/漏极区域中的凸部的侧表面相邻的第二间隔物。

3. 发明申请

US20090174036A1 PLASMA CURING OF PATTERNING MATERIALS FOR AGGRESSIVELY SCALED FEATURES 审中-公开
标题翻译：等离子体固化材料的等离子体刻蚀特性
公开(公告)号：US20090174036A1
公开(公告)日：2009-07-09
申请号：US11969525
申请日：2008-01-04
申请人： Nicholas C. Fuller , Michael A. Guillorn , Hirohisa Kawasaki , Atsushi Yagishita
发明人： Nicholas C. Fuller , Michael A. Guillorn , Hirohisa Kawasaki , Atsushi Yagishita
IPC分类号： H01L29/30 , G03F7/26
CPC分类号： G03F7/40
摘要： A methodology is disclosed that enables the fabrication of semiconductor devices (i.e., STI structures, gates, and interconnects) with significantly reduced line edge roughness (LER) and line width roughness (LEW) post lithography patterning. The inventive methodology entails the use of an inert species containing plasma tuned to enhanced its' vacuum ultra violet (VUV) emissions post lithography and/or post one of the etch processes of a given feature (on an identical etch platform) to entice increased crosslinking of one or more patterning materials, thus enabling increased etch resistance and reduced LER and LEW post etching processing.
摘要翻译：公开了一种能够在光刻图案化之后显着降低线边缘粗糙度（LER）和线宽粗糙度（LEW）来制造半导体器件（即STI结构，栅极和互连）的方法。本发明的方法需要使用含有等离子体的惰性物质来调整光刻后的真空紫外（VUV）发射和/或给定特征（在相同的蚀刻平台上）的一个蚀刻工艺，以引发增加的交联的一个或多个图案形成材料，因此能够提高耐蚀刻性和减少LER和LEW后蚀刻处理。

4. 发明申请

US20110260282A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHODS 审中-公开
标题翻译：半导体器件和制造方法
公开(公告)号：US20110260282A1
公开(公告)日：2011-10-27
申请号：US12766367
申请日：2010-04-23
申请人： Hirohisa Kawasaki
发明人： Hirohisa Kawasaki
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L29/66795 , H01L21/76229
摘要： Methods of making fins and semiconductor structures containing fins are provided. The methods involve forming a multi-layer structure over fins and isolation materials and performing a multi-stage etching process to remove upper portions of the multi-layer structure and upper portions of isolation materials. Upper portions of the fins are exposed by removing the upper portions of the isolation materials via the multi-stage etching process. A stage of the multi-stage etching process removes an upper layer of the multi-layer structure and an upper portion of the isolation materials, and the stage can be terminated about at the same time when the upper surface of the underlying layer of the multi-layer structure is exposed.
摘要翻译：提供制造散热片和包含散热片的半导体结构的方法。所述方法包括在鳍片和隔离材料上形成多层结构，并执行多级蚀刻工艺以去除多层结构的上部和隔离材料的上部。通过多级蚀刻工艺除去隔离材料的上部，使翅片的上部露出。多级蚀刻工艺的阶段除去多层结构的上层和隔离材料的上部，并且阶段可以在多层的下层的下表面的同时终止层结构暴露。

5. 发明授权

US08809830B2 Variable resistance memory 有权
标题翻译：可变电阻记忆
公开(公告)号：US08809830B2
公开(公告)日：2014-08-19
申请号：US13425668
申请日：2012-03-21
申请人： Hirohisa Kawasaki
发明人： Hirohisa Kawasaki
IPC分类号： H01L45/00
CPC分类号： H01L45/1266 , H01L45/085 , H01L45/1233 , H01L45/14 , H01L45/148
摘要： A variable resistance memory according to the present embodiment includes a memory cell including an ion source electrode including metal atoms, an opposite electrode, an amorphous silicon film formed between the ion source electrode and the opposite electrode, and a polysilicon film formed between the amorphous silicon film and the ion source electrode.
摘要翻译：根据本实施例的可变电阻存储器包括：存储单元，包括具有金属原子的离子源电极，相对电极，形成在离子源电极和相对电极之间的非晶硅膜;以及形成在非晶硅之间的多晶硅膜膜和离子源电极。

6. 发明申请

US20120193751A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120193751A1
公开(公告)日：2012-08-02
申请号：US13015857
申请日：2011-01-28
申请人： Hirohisa Kawasaki , Basker Veeraraghavan , Hemant Adhikari , Witold Maszara
发明人： Hirohisa Kawasaki , Basker Veeraraghavan , Hemant Adhikari , Witold Maszara
IPC分类号： H01L29/06 , H01L21/20
CPC分类号： H01L29/66795 , H01L29/785
摘要： Methods of making fins and semiconductor structures containing fins are provided. The methods involve forming a multi-layer structure over a semiconductor substrate. The multi-layer structure comprises a first layer over the semiconductor substrate, a second layer over the first layer, and a third layer over the second layer. The method also comprises removing upper portions of the semiconductor substrate and portions of the multi-layer structure to form fins of the semiconductor substrate and portions of the multi-layer structure. Further, the method comprises selectively oxidizing the first layer while oxidization of the second layer and the third layer is less than the oxidization of the first layer. The oxidation can be performed before gap fill recess or after gap fill recess.
摘要翻译：提供制造散热片和包含散热片的半导体结构的方法。所述方法包括在半导体衬底上形成多层结构。多层结构包括半导体衬底上的第一层，第一层上的第二层和第二层上的第三层。该方法还包括去除半导体衬底的上部和多层结构的部分以形成半导体衬底的鳍片和多层结构的部分。此外，该方法包括选择性地氧化第一层，同时氧化第二层，第三层小于第一层的氧化。可以在间隙填充凹部之前或间隙填充凹部之后进行氧化。

7. 发明授权

US07164175B2 Semiconductor device with silicon-film fins and method of manufacturing the same 失效
标题翻译：具有硅膜翅片的半导体器件及其制造方法
公开(公告)号：US07164175B2
公开(公告)日：2007-01-16
申请号：US10835122
申请日：2004-04-28
申请人： Hirohisa Kawasaki , Kazunari Ishimaru
发明人： Hirohisa Kawasaki , Kazunari Ishimaru
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0207 , H01L27/11 , H01L27/1108 , H01L27/1211 , H01L29/66795
摘要： A semiconductor device includes a semiconductor substrate, an insulating film projected on a surface of the semiconductor substrate, a semiconductor film provided on a side surface of the insulating film, and MIS transistor formed in the semiconductor film, the MIS transistor having source, gate and drain region. The semiconductor device further includes a gate electrode provided on the gate region of the MIS transistor, the length of the gate electrode being larger than the thickness of the semiconductor film.
摘要翻译：半导体器件包括半导体衬底，投影在半导体衬底的表面上的绝缘膜，设置在绝缘膜的侧表面上的半导体膜和形成在半导体膜中的MIS晶体管，所述MIS晶体管具有源极，栅极和漏区。半导体器件还包括设置在MIS晶体管的栅极区上的栅电极，栅电极的长度大于半导体膜的厚度。

8. 发明授权

US08859389B2 Methods of making fins and fin field effect transistors (FinFETs) 有权
标题翻译：制造鳍片和鳍场效应晶体管（FinFET）的方法
公开(公告)号：US08859389B2
公开(公告)日：2014-10-14
申请号：US13015857
申请日：2011-01-28
申请人： Hirohisa Kawasaki , Basker Veeraraghavan , Hemant Adhikari , Witold Maszara
发明人： Hirohisa Kawasaki , Basker Veeraraghavan , Hemant Adhikari , Witold Maszara
IPC分类号： H01L21/76 , H01L21/336 , H01L21/8234 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66795 , H01L29/785
摘要： Methods of making fins and semiconductor structures containing fins are provided. The methods involve forming a multi-layer structure over a semiconductor substrate. The multi-layer structure comprises a first layer over the semiconductor substrate, a second layer over the first layer, and a third layer over the second layer. The method also comprises removing upper portions of the semiconductor substrate and portions of the multi-layer structure to form fins of the semiconductor substrate and portions of the multi-layer structure. Further, the method comprises selectively oxidizing the first layer while oxidization of the second layer and the third layer is less than the oxidization of the first layer. The oxidation can be performed before gap fill recess or after gap fill recess.
摘要翻译：提供制造散热片和包含散热片的半导体结构的方法。所述方法包括在半导体衬底上形成多层结构。多层结构包括半导体衬底上的第一层，第一层上的第二层和第二层上的第三层。该方法还包括去除半导体衬底的上部和多层结构的部分以形成半导体衬底的鳍片和多层结构的部分。此外，该方法包括选择性地氧化第一层，同时氧化第二层，第三层小于第一层的氧化。可以在间隙填充凹部之前或间隙填充凹部之后进行氧化。

9. 发明申请

US20130075686A1 VARIABLE RESISTANCE MEMORY 有权
公开(公告)号：US20130075686A1
公开(公告)日：2013-03-28
申请号：US13425668
申请日：2012-03-21
申请人： Hirohisa Kawasaki
发明人： Hirohisa Kawasaki
IPC分类号： H01L45/00
CPC分类号： H01L45/1266 , H01L45/085 , H01L45/1233 , H01L45/14 , H01L45/148
摘要： A variable resistance memory according to the present embodiment includes a memory cell including an ion source electrode including metal atoms, an opposite electrode, an amorphous silicon film formed between the ion source electrode and the opposite electrode, and a polysilicon film formed between the amorphous silicon film and the ion source electrode.

10. 发明申请

US20110298058A1 FACETED EPI SHAPE AND HALF-WRAP AROUND SILICIDE IN S/D MERGED FINFET 有权
标题翻译： S / D合并FINFET中的硅化物表面形状和厚度
公开(公告)号：US20110298058A1
公开(公告)日：2011-12-08
申请号：US12794151
申请日：2010-06-04
申请人： Hirohisa Kawasaki , Chung-hsun Lin
发明人： Hirohisa Kawasaki , Chung-hsun Lin
IPC分类号： H01L27/085 , H01L21/70
CPC分类号： H01L29/7853 , H01L29/66795
摘要： FinFETs and methods of making. FinFETs are provided. The FinFET contains two or more fins over a semiconductor substrate; two or more epitaxial layers over side surfaces of the fins; and metal-semiconductor compounds over an upper surfaces of the epitaxial layers. The fin has side surfaces that are substantially vertical relative to the upper surface of the semiconductor substrate. The epitaxial layer has an upper surface that extends at an oblique angle with respect to the side surface of the fin. The FinFET can contain a contact over the metal-semiconductor compounds.
摘要翻译： FinFET和制作方法。提供FinFET。 FinFET在半导体衬底上包含两个或更多个鳍; 在翅片的侧表面上的两个或更多个外延层; 和在外延层的上表面上的金属 - 半导体化合物。翅片具有相对于半导体衬底的上表面基本垂直的侧表面。外延层具有相对于鳍的侧表面以倾斜角度延伸的上表面。 FinFET可以包含金属 - 半导体化合物上的接触。

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