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1. 发明申请

US20050201177A1 Nonvolatile memory apparatus 有权
标题翻译：非易失存储器
公开(公告)号：US20050201177A1
公开(公告)日：2005-09-15
申请号：US11076563
申请日：2005-03-10
申请人： Atsushi Shiraishi , Atsushi Shikata , Yasuhiro Nakamura , Makoto Obata
发明人： Atsushi Shiraishi , Atsushi Shikata , Yasuhiro Nakamura , Makoto Obata
IPC分类号： G06F12/16 , G06F3/06 , G06F3/08 , G11C5/00 , G11C16/06
CPC分类号： G11C16/105 , G06F11/1441
摘要： The present invention is directed to suppress data loss caused by power shut-down during a rewriting process and to shorten time required to make a depletion check. A nonvolatile memory apparatus includes a rewritable nonvolatile memory and a card controller. The nonvolatile memory has a physical address area corresponding to a logical address and a save area. In response to a data rewrite instruction on a required logical address, the card controller stores data in a predetermined physical address area corresponding to the logical address to the save area and rewrites the data stored in the physical address area. When rewriting of the physical address area is incomplete, the card controller rewrites the data in the physical address area with the data stored in the save area. Thus, data loss caused by the power shut-down can be suppressed by data backup, and it is sufficient to make the depletion check in two places of the save area and the physical address area.
摘要翻译：本发明旨在抑制在重写处理期间由电源关闭引起的数据丢失并且缩短进行耗尽检查所需的时间。非易失性存储装置包括可重写非易失性存储器和卡控制器。非易失性存储器具有对应于逻辑地址和保存区域的物理地址区域。响应于所需逻辑地址上的数据重写指令，卡控制器将数据存储在与逻辑地址相对应的预定物理地址区域中并重写存储在物理地址区域中的数据。当重写物理地址区域不完整时，卡控制器使用存储在保存区域中的数据重写物理地址区域中的数据。因此，可以通过数据备份来抑制由电源关闭引起的数据丢失，并且在存储区域和物理地址区域的两个位置进行耗尽检查是足够的。

2. 发明授权

US07330995B2 Nonvolatile memory apparatus which prevents destruction of write data caused by power shutdown during a writing process 有权
标题翻译：非易失性存储装置，其防止在写入过程期间由电源关闭引起的写入数据的破坏
公开(公告)号：US07330995B2
公开(公告)日：2008-02-12
申请号：US11076563
申请日：2005-03-10
申请人： Atsushi Shiraishi , Atsushi Shikata , Yasuhiro Nakamura , Makoto Obata
发明人： Atsushi Shiraishi , Atsushi Shikata , Yasuhiro Nakamura , Makoto Obata
IPC分类号： G06F11/00
CPC分类号： G11C16/105 , G06F11/1441
摘要： The present invention is directed to suppress data loss caused by power shut-down during a rewriting process and to shorten time required to make a depletion check.A nonvolatile memory apparatus includes a rewritable nonvolatile memory and a card controller. The nonvolatile memory has a physical address area corresponding to a logical address and a save area. In response to a data rewrite instruction on a required logical address, the card controller stores data in a predetermined physical address area corresponding to the logical address to the save area and rewrites the data stored in the physical address area. When rewriting of the physical address area is incomplete, the card controller rewrites the data in the physical address area with the data stored in the save area. Thus, data loss caused by the power shut-down can be suppressed by data backup, and it is sufficient to make the depletion check in two places of the save area and the physical address area.
摘要翻译：本发明旨在抑制在重写处理期间由电源关闭引起的数据丢失并且缩短进行耗尽检查所需的时间。非易失性存储装置包括可重写非易失性存储器和卡控制器。非易失性存储器具有对应于逻辑地址和保存区域的物理地址区域。响应于所需逻辑地址上的数据重写指令，卡控制器将数据存储在对应于逻辑地址的预定物理地址区域中并重写存储在物理地址区中的数据。当重写物理地址区域不完整时，卡控制器使用存储在保存区域中的数据重写物理地址区域中的数据。因此，可以通过数据备份来抑制由电源关闭引起的数据丢失，并且在存储区域和物理地址区域的两个位置进行耗尽检查是足够的。

3. 发明授权

US06917547B2 Non-volatile semiconductor memory device 有权
公开(公告)号：US06917547B2
公开(公告)日：2005-07-12
申请号：US10616955
申请日：2003-07-11
申请人： Motoki Kanamori , Kunihiro Katayama , Atsushi Shiraishi , Shigeo Kurakata , Atsushi Shikata
发明人： Motoki Kanamori , Kunihiro Katayama , Atsushi Shiraishi , Shigeo Kurakata , Atsushi Shikata
IPC分类号： G06F12/16 , G06F11/00 , G06F11/10 , G11C16/06 , G11C29/00 , G11C29/42 , G11C7/00
CPC分类号： G11C29/76 , G06F11/1068 , G11C16/04 , G11C16/3431 , G11C29/765 , G11C29/81 , G11C29/82 , G11C2029/0411
摘要： When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.

4. 发明授权

US07102943B2 Non-volatile semiconductor memory device 有权
公开(公告)号：US07102943B2
公开(公告)日：2006-09-05
申请号：US11152101
申请日：2005-06-15
申请人： Motoki Kanamori , Kunihiro Katayama , Atsushi Shiraishi , Shigeo Kurakata , Atsushi Shikata
发明人： Motoki Kanamori , Kunihiro Katayama , Atsushi Shiraishi , Shigeo Kurakata , Atsushi Shikata
IPC分类号： G11C7/00
CPC分类号： G11C29/76 , G06F11/1068 , G11C16/04 , G11C16/3431 , G11C29/765 , G11C29/81 , G11C29/82 , G11C2029/0411
摘要： When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.

5. 发明授权

US06608784B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06608784B2
公开(公告)日：2003-08-19
申请号：US10078471
申请日：2002-02-21
申请人： Motoki Kanamori , Kunihiro Katayama , Atsushi Shiraishi , Shigeo Kurakata , Atsushi Shikata
发明人： Motoki Kanamori , Kunihiro Katayama , Atsushi Shiraishi , Shigeo Kurakata , Atsushi Shikata
IPC分类号： G11C1606
CPC分类号： G11C29/76 , G06F11/1068 , G11C16/04 , G11C16/3431 , G11C29/765 , G11C29/81 , G11C29/82 , G11C2029/0411
摘要： When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.
摘要翻译：当在包含非易失性存储器和纠错电路的卡存储装置中发生非易失性存储器写入错误时，从非易失性存储器读取写入数据，并且检查错误是否可以通过错误来校正校正电路。如果可以纠正错误，则写入操作结束。如果纠错电路无法纠正错误，则执行替代处理以将数据写入其他区域。

6. 发明授权

US07403436B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07403436B2
公开(公告)日：2008-07-22
申请号：US11453926
申请日：2006-06-16
申请人： Motoki Kanamori , Kunihiro Katayama , Atsushi Shiraishi , Shigeo Kurakata , Atsushi Shikata
发明人： Motoki Kanamori , Kunihiro Katayama , Atsushi Shiraishi , Shigeo Kurakata , Atsushi Shikata
IPC分类号： G11C7/00
CPC分类号： G11C29/76 , G06F11/1068 , G11C16/04 , G11C16/3431 , G11C29/765 , G11C29/81 , G11C29/82 , G11C2029/0411
摘要： When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.
摘要翻译：当在包含非易失性存储器和纠错电路的卡存储装置中发生非易失性存储器写入错误时，从非易失性存储器读取写入数据，并且检查错误是否可以通过错误来校正校正电路。如果可以纠正错误，则写入操作结束。如果纠错电路无法纠正错误，则执行替代处理以将数据写入其他区域。

7. 发明申请

US20070033334A1 Non-volatile memory card and transfer interruption means 有权
标题翻译：非易失性存储卡和传输中断手段
公开(公告)号：US20070033334A1
公开(公告)日：2007-02-08
申请号：US11541543
申请日：2006-10-03
申请人： Kunihiro Katayama , Motoki Kanamori , Atsushi Shikata , Hidefumi Oodate , Atsushi Shiraishi
发明人： Kunihiro Katayama , Motoki Kanamori , Atsushi Shikata , Hidefumi Oodate , Atsushi Shiraishi
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06K19/07 , G11C16/102
摘要： A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition. Consequently, even when the timing signal not conforming to the standards is transferred, the host can select the optimum processing operation from the internal processing conditions and thereby execute the selected operation.
摘要翻译：存储卡设置有传送控制电路，写入控制电路和判断电路。传送控制电路在数据传送期间输出传送标志信号。写入控制电路在数据写入操作期间输出内部忙信号。当输入传送平面信号期间主机的卡选择信号被否定时，判断电路输出传送中断信号，并且当在内部忙信号的输入期间卡选择信号被否定时，输出暂停信号。 CPU在接收到传送中断信号时使传送数据中断传输处理，并且在接收到暂停信号时完成正在执行的处理并处于等待状态。因此，即使当不符合标准的定时信号被传送时，主机也可以从内部处理条件中选择最佳处理操作，从而执行所选择的操作。

8. 发明申请

US20060233032A1 Non-volatile semiconductor memory device 失效
公开(公告)号：US20060233032A1
公开(公告)日：2006-10-19
申请号：US11453926
申请日：2006-06-16
申请人： Motoki Kanamori , Kunihiro Katayama , Atsushi Shiraishi , Shigeo Kurakata , Atsushi Shikata
发明人： Motoki Kanamori , Kunihiro Katayama , Atsushi Shiraishi , Shigeo Kurakata , Atsushi Shikata
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/76 , G06F11/1068 , G11C16/04 , G11C16/3431 , G11C29/765 , G11C29/81 , G11C29/82 , G11C2029/0411
摘要： When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.

9. 发明申请

US20050246574A1 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050246574A1
公开(公告)日：2005-11-03
申请号：US11152101
申请日：2005-06-15
申请人： Motoki Kanamori , Kunihiro Katayama , Atsushi Shiraishi , Shigeo Kurakata , Atsushi Shikata
发明人： Motoki Kanamori , Kunihiro Katayama , Atsushi Shiraishi , Shigeo Kurakata , Atsushi Shikata
IPC分类号： G06F12/16 , G06F11/00 , G06F11/10 , G11C16/06 , G11C29/00 , G11C29/42
CPC分类号： G11C29/76 , G06F11/1068 , G11C16/04 , G11C16/3431 , G11C29/765 , G11C29/81 , G11C29/82 , G11C2029/0411
摘要： When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.
摘要翻译：当在包含非易失性存储器和纠错电路的卡存储装置中发生非易失性存储器写入错误时，从非易失性存储器读取写入数据，并且检查错误是否可以通过错误来校正校正电路。如果可以纠正错误，则写入操作结束。如果纠错电路无法纠正错误，则执行替代处理以将数据写入其他区域。

10. 发明授权

US07343445B2 Non-volatile memory card and transfer interruption means 有权
标题翻译：非易失性存储卡和传输中断手段
公开(公告)号：US07343445B2
公开(公告)日：2008-03-11
申请号：US11541543
申请日：2006-10-03
申请人： Kunihiro Katayama , Motoki Kanamori , Atsushi Shikata , Hidefumi Oodate , Atsushi Shiraishi
发明人： Kunihiro Katayama , Motoki Kanamori , Atsushi Shikata , Hidefumi Oodate , Atsushi Shiraishi
IPC分类号： G06F12/00
CPC分类号： G06K19/07 , G11C16/102
摘要： A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition. Consequently, even when the timing signal not conforming to the standards is transferred, the host can select the optimum processing operation from the internal processing conditions and thereby execute the selected operation.
摘要翻译：存储卡设置有传送控制电路，写入控制电路和判断电路。传送控制电路在数据传送期间输出传送标志信号。写入控制电路在数据写入操作期间输出内部忙信号。当输入传送平面信号期间主机的卡选择信号被否定时，判断电路输出传送中断信号，并且当在内部忙信号的输入期间卡选择信号被否定时，输出暂停信号。 CPU在接收到传送中断信号时使传送数据中断传输处理，并且在接收到暂停信号时完成正在执行的处理并处于等待状态。因此，即使当不符合标准的定时信号被传送时，主机也可以从内部处理条件中选择最佳处理操作，从而执行所选择的操作。

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