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1. 发明申请

US20100054025A1 SEMICONDUCTOR INTEGRATED MEMORY CIRCUIT AND TRIMMING METHOD THEREOF 有权
标题翻译：半导体集成存储器电路及其研制方法
公开(公告)号：US20100054025A1
公开(公告)日：2010-03-04
申请号：US12540022
申请日：2009-08-12
申请人： Atsushi Kawasumi , Yukihiro Urakawa
发明人： Atsushi Kawasumi , Yukihiro Urakawa
IPC分类号： G11C11/00 , G11C5/14 , G11C7/02
CPC分类号： G11C7/1045 , G11C7/065 , G11C11/412
摘要： A latch circuit includes first and second inverters connected in a cross-coupling manner at a first node and a second node. A voltage application circuit applies a hot carrier generation voltage for generating hot carrier at a transistor included in the first inverter or the second inverter. An inverting circuit generates an inversion signal as an inverted signal of an amplified signal provided from the latch circuit to the bit line pair to provide the inversion signal to the first node and the second node.
摘要翻译：锁存电路包括在第一节点和第二节点处以交叉耦合方式连接的第一和第二反相器。电压施加电路在包含在第一逆变器或第二逆变器中的晶体管上施加用于产生热载流子的热载流子产生电压。反相电路产生作为从锁存电路向位线对提供的放大信号的反相信号的反相信号，以向第一节点和第二节点提供反转信号。

2. 发明授权

US08018757B2 Semiconductor memory device and trimming method thereof 有权
标题翻译：半导体存储器件及其修整方法
公开(公告)号：US08018757B2
公开(公告)日：2011-09-13
申请号：US12539883
申请日：2009-08-12
申请人： Atsushi Kawasumi , Yukihiro Urakawa
发明人： Atsushi Kawasumi , Yukihiro Urakawa
IPC分类号： G11C11/00
CPC分类号： G11C7/02 , G11C5/147 , G11C11/41 , G11C11/413 , G11C11/417 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/50 , G11C2207/2254
摘要： The first power supply terminal is connected to source electrodes of the first and third transistors. The second power supply terminal is connected to source electrodes of the second and fourth transistors. When offset information of the memory cell is to be read, a voltage applied to the first power supply terminal and a voltage applied to the second power supply terminal are made equal. Then the voltage applied to the first power supply terminal is returned to the first potential, and the voltage applied to the second power supply terminal is returned to the second potential. When stress is generated in the first to fourth transistor included in the first or second inverter, the potential difference between the first power supply terminal and the second power supply terminal is made larger than a difference between the first potential and the second potential.
摘要翻译：第一电源端子连接到第一和第三晶体管的源电极。第二电源端子连接到第二和第四晶体管的源电极。当要读取存储器单元的偏移信息时，施加到第一电源端子的电压和施加到第二电源端子的电压相等。然后，施加到第一电源端子的电压返回到第一电位，并且施加到第二电源端子的电压返回到第二电位。当在包括在第一或第二逆变器中的第一至第四晶体管中产生应力时，使得第一电源端子和第二电源端子之间的电位差大于第一电位和第二电位之间的差。

3. 发明授权

US08077499B2 Semiconductor integrated memory circuit and trimming method thereof 有权
标题翻译：半导体集成存储电路及其修整方法
公开(公告)号：US08077499B2
公开(公告)日：2011-12-13
申请号：US12540022
申请日：2009-08-12
申请人： Atsushi Kawasumi , Yukihiro Urakawa
发明人： Atsushi Kawasumi , Yukihiro Urakawa
IPC分类号： G11C11/00
CPC分类号： G11C7/1045 , G11C7/065 , G11C11/412
摘要： A latch circuit includes first and second inverters connected in a cross-coupling manner at a first node and a second node. A voltage application circuit applies a hot carrier generation voltage for generating hot carrier at a transistor included in the first inverter or the second inverter. An inverting circuit generates an inversion signal as an inverted signal of an amplified signal provided from the latch circuit to the bit line pair to provide the inversion signal to the first node and the second node.
摘要翻译：锁存电路包括在第一节点和第二节点处以交叉耦合方式连接的第一和第二反相器。电压施加电路在包含在第一逆变器或第二逆变器中的晶体管上施加用于产生热载流子的热载流子产生电压。反相电路产生作为从锁存电路向位线对提供的放大信号的反相信号的反相信号，以向第一节点和第二节点提供反转信号。

4. 发明授权

US08338964B2 Stacked-chip device 有权
公开(公告)号：US08338964B2
公开(公告)日：2012-12-25
申请号：US13419100
申请日：2012-03-13
申请人： Yukihiro Urakawa
发明人： Yukihiro Urakawa
IPC分类号： H01L23/522
CPC分类号： H01L25/0657 , H01L23/645 , H01L24/48 , H01L24/49 , H01L28/10 , H01L2224/32145 , H01L2224/48091 , H01L2224/49175 , H01L2225/06513 , H01L2225/06527 , H01L2924/00014 , H01L2924/15311 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A stacked-chip device includes a first inductive chip having a first function, a second inductive chip having a second function different from the first function, which is stacked on the first inductive chip, and a third inductive chip having the second function, which is stacked on the second inductive chip. Each of the first, second and third inductive chips has transmitting inductors which transmit data and receiving inductors which receive data. The transmitting inductors and the receiving inductors are disposed in line symmetry to an axis of symmetry. The axes of symmetry of the first, second and third inductive chips are overlapped. Each of the second and third inductive chips is disposed in upside-down or back to front to the first inductive chip.

5. 发明授权

US08000923B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08000923B2
公开(公告)日：2011-08-16
申请号：US12043584
申请日：2008-03-06
申请人： Takashi Inukai , Yukihiro Urakawa
发明人： Takashi Inukai , Yukihiro Urakawa
IPC分类号： G01K15/00
CPC分类号： G01K15/002 , G01K7/425
摘要： A semiconductor integrated circuit according to the examples of the present invention is applied to a system using a first power source voltage and a second power source voltage independent of the first power source voltage and includes a first area to which the first power source voltage is supplied, a thermal sensor placed in the first area, and a first input path placed in the first area, for transferring trimming data that determine the control contents of the thermal sensor to the thermal sensor.
摘要翻译：根据本发明的实施例的半导体集成电路被应用于使用与第一电源电压无关的第一电源电压和第二电源电压的系统，并且包括提供第一电源电压的第一区域放置在第一区域中的热传感器和放置在第一区域中的第一输入路径，用于将确定热传感器的控制内容的修整数据传送到热传感器。

6. 发明授权

US07525132B2 Semiconductor integrated circuit wiring design method and semiconductor integrated circuit 失效
标题翻译：半导体集成电路布线设计方法和半导体集成电路
公开(公告)号：US07525132B2
公开(公告)日：2009-04-28
申请号：US11670568
申请日：2007-02-02
申请人： Shinji Kitabayashi , Yukihiro Urakawa
发明人： Shinji Kitabayashi , Yukihiro Urakawa
IPC分类号： H01L27/10
CPC分类号： G06F17/5077 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： The facility of operation in a manufacturing process and the reliability of the finished product can be improved by making a design based on two basic wiring pattern layers in which wiring traces are formed with regularity, and a basic via array layer inserted between the two basic wiring pattern layers, in which vias are formed with regularity.
摘要翻译：可以通过基于布置有规则性的两个基本布线图案层进行设计来改进制造工艺中的操作设备和成品的可靠性，以及插入在两个基本布线之间的基本通孔阵列层图案层，其中通孔形成规则性。

7. 发明授权

US07353481B2 Computer implemented method for designing a semiconductor integrated circuit and a semiconductor integrated circuit 失效
标题翻译：用于设计半导体集成电路和半导体集成电路的计算机实现方法
公开(公告)号：US07353481B2
公开(公告)日：2008-04-01
申请号：US11320643
申请日：2005-12-30
申请人： Koichi Kinoshita , Yukihiro Urakawa
发明人： Koichi Kinoshita , Yukihiro Urakawa
IPC分类号： G06F17/50 , H01L25/00 , H03L19/00 , H03H1/00 , H03H2/00
CPC分类号： G06F17/5068 , H01L23/522 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A computer implemented method for designing a semiconductor integrated circuit includes placing dummy pattern on a second interconnection layer positioned just above the first power line based on a placement result of the first power line, the dummy pattern having a long axis parallel with a direction of the first power line; and electrically connecting the dummy pattern to the first power line, based on placement results of the first power line and the dummy pattern.
摘要翻译：一种用于设计半导体集成电路的计算机实现方法包括：基于第一电力线的放置结果，将伪图案放置在位于第一电力线正上方的第二互连层上，虚设图案具有与第一电力线的方向平行的长轴第一电力线; 并且基于第一电力线和虚拟图案的配置结果，将虚设图案电连接到第一电力线。

8. 发明申请

US20060224351A1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US20060224351A1
公开(公告)日：2006-10-05
申请号：US11261536
申请日：2005-10-31
申请人： Takashi Inukai , Yukihiro Urakawa
发明人： Takashi Inukai , Yukihiro Urakawa
IPC分类号： G01K1/08
CPC分类号： G01K15/002 , G01K7/425
摘要： A semiconductor integrated circuit according to the examples of the present invention is applied to a system using a first power source voltage and a second power source voltage independent of the first power source voltage and includes a first area to which the first power source voltage is supplied, a thermal sensor placed in the first area, and a first input path placed in the first area, for transferring trimming data that determine the control contents of the thermal sensor to the thermal sensor.
摘要翻译：根据本发明的实施例的半导体集成电路被应用于使用与第一电源电压无关的第一电源电压和第二电源电压的系统，并且包括提供第一电源电压的第一区域放置在第一区域中的热传感器和放置在第一区域中的第一输入路径，用于将确定热传感器的控制内容的修整数据传送到热传感器。

9. 发明申请

US20050134300A1 Semiconductor integrated circuit and method for testing a semiconductor integrated circuit 失效
标题翻译：半导体集成电路和半导体集成电路测试方法
公开(公告)号：US20050134300A1
公开(公告)日：2005-06-23
申请号：US11001155
申请日：2004-12-02
申请人： Natsuki Kushiyama , Yukihiro Urakawa
发明人： Natsuki Kushiyama , Yukihiro Urakawa
IPC分类号： G01R31/28 , G01R31/02 , G01R31/30 , G01R31/317 , H01L21/822 , H01L27/04
CPC分类号： G01R31/31725 , G01R31/3016
摘要： A semiconductor integrated circuit includes a first delay circuit generating a first delay clock; a second delay circuit generating a second delay clock; a first register registering a value of a first delay of the first delay clock; a second register registering a value of a second delay of the second delay clock; a clock supplying circuit supplying a clock signal to the first and second delay circuits; a phase comparator detecting a phase difference between the first and second delay clocks; and a built-in test circuit configured to control the first and second registers so that the value of the first delay can be registered in the first register and the value of the second delay can be registered in the second register.
摘要翻译：半导体集成电路包括产生第一延迟时钟的第一延迟电路; 产生第二延迟时钟的第二延迟电路; 注册第一延迟时钟的第一延迟值的第一寄存器; 第二寄存器，其记录所述第二延迟时钟的第二延迟值; 时钟供给电路，向第一和第二延迟电路提供时钟信号; 相位比较器，检测第一和第二延迟时钟之间的相位差; 以及内置测试电路，被配置为控制第一和第二寄存器，使得可以将第一延迟的值登记在第一寄存器中，并且可以将第二延迟的值登记在第二寄存器中。

10. 发明授权

US5517454A Semiconductor memory device having refresh circuits 失效
标题翻译：具有刷新电路的半导体存储器件
公开(公告)号：US5517454A
公开(公告)日：1996-05-14
申请号：US355762
申请日：1994-12-14
申请人： Katsuhiko Sato , Kiyofumi Ochii , Yukihiro Urakawa
发明人： Katsuhiko Sato , Kiyofumi Ochii , Yukihiro Urakawa
IPC分类号： G11C11/405 , G11C11/403 , G11C11/406 , G11C11/409 , G11C7/00
CPC分类号： G11C11/406
摘要： A semiconductor memory device including dynamic memory cells for which refresh operation is required, wherein one fundamental cycle consists of a normal operation for carrying out writing or reading into or from the memory cells and a refresh operation. This semiconductor memory device comprising: a refresh signal generating circuit supplied with a clock signal to generate a refresh signal indicating start of refresh; a count signal generating circuit supplied with the clock signal to generate a count signal required for selection of a memory cell to be refreshed, a refresh counter circuit supplied with the refresh signal and the count signal to select a word line and a bit line to which a memory cell to be refreshed is connected; and a precharge circuit supplied with the refresh signal to carry out precharge of the bit line for refresh.
摘要翻译：一种包括需要刷新操作的动态存储器单元的半导体存储器件，其中一个基本周期包括用于执行对存储器单元的写入或读取的正常操作和刷新操作。该半导体存储器件包括：刷新信号发生电路，被提供有时钟信号以产生指示刷新开始的刷新信号; 提供有时钟信号的计数信号发生电路，以产生选择要刷新的存储单元所需的计数信号，提供有刷新信号的刷新计数器电路和计数信号以选择字线和位线连接要更新的存储单元; 以及提供有刷新信号的预充电电路，以执行用于刷新的位线的预充电。

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