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    • 1. 发明授权
    • Modulation method, modulation apparatus, demodulation method, demodulation apparatus, information recording medium, information transmission method, and information transmission apparatus
    • 调制方法,调制装置,解调方法,解调装置,信息记录介质,信息发送方法和信息发送装置
    • US06653952B2
    • 2003-11-25
    • US10160023
    • 2002-06-04
    • Atsushi HayamiToshio KuroiwaTsuyoshi Oki
    • Atsushi HayamiToshio KuroiwaTsuyoshi Oki
    • H03M700
    • H03M5/145G11B20/1426G11B2020/1282G11B2020/1284G11B2020/143G11B2020/1457H03M7/46
    • There is disclosed a modulation method in which a four bit unit of a plurality of continuous input data words is encoded into a six bit unit of a plurality of continuous output code words by referring to a plurality of coding tables including output code words corresponding to input data words, and coding table designation information in which a coding table for use in encoding the next input data word is designated. The plurality of coding tables includes at least a first coding table and a second coding table, and first and second signals respectively obtained by subjecting a first output code word of said first coding table corresponding to a predetermined input data word and a second output code word of said second coding table corresponding to said predetermined input data word to NRZI modulation are reverse to each other in polarity. Further, in particular, two redundant bits are inserted into the plurality of continuous output code words for each predetermined number of corresponding data words. Even with such redundant bits, a DSV control is performed in any section, k satisfies 9 in a (1, k) RLL rule, and a repetition frequency of a minimum run is limited.
    • 公开了一种调制方法,其中通过参考包括与输入对应的输出代码字的多个编码表,将多个连续输入数据字中的四位单位编码为多个连续输出代码字的六位单元 数据字和编码表指定信息,其中指定用于编码下一个输入数据字的编码表。 多个编码表至少包括第一编码表和第二编码表,以及分别通过对与预定输入数据字对应的所述第一编码表的第一输出代码字和第二输出代码字 对应于所述预定输入数据字到NRZI调制的所述第二编码表的极性相反。 此外,特别地,对于每个预定数量的相应数据字,两个冗余比特被插入到多个连续输出码字中。 即使使用这样的冗余比特,在任何部分都执行DSV控制,在(1,k)RLL规则中k满足9,并且限制最小运行的重复频率。
    • 3. 发明授权
    • Method and apparatus for encoding digital data
    • 用于编码数字数据的方法和装置
    • US06577255B2
    • 2003-06-10
    • US10270537
    • 2002-10-16
    • Atsushi HayamiToshio Kuroiwa
    • Atsushi HayamiToshio Kuroiwa
    • H03M700
    • H03M5/145G11B20/1426G11B20/18G11B2020/1457H03M7/46
    • Encoding tables are accorded with variable-length encoding rules using a variable constraint length. A DSV control bit is periodically inserted into a first input bit stream to generate a second input bit stream. Every m-bit piece of the second input bit stream is encoded into an n-bit output signal forming at least a portion of an output code word by referring to the encoding tables. Thereby, the second input bit stream is converted into a first output bit stream composed of output code words and observing RLL (d, k). A sync word is inserted into the first output bit stream for every frame to generate a second output bit stream. A frame-end output code word is terminated at a position before a next-frame sync word. DSV control of the second output bit stream is implemented in response to the inserted DSV control bits.
    • 编码表符合使用可变约束长度的可变长度编码规则。 周期性地将DSV控制位插入到第一输入位流中以产生第二输入位流。 通过参照编码表将第二输入比特流的每个m位片段编码成形成输出码字的至少一部分的n位输出信号。 由此,第二输入比特流被转换成由输出码字组成的第一输出比特流并观察RLL(d,k)。 对于每一帧,将同步字插入到第一输出比特流中以产生第二输出比特流。 帧结束输出码字在下一帧同步字之前的位置终止。 响应于插入的DSV控制位来实现第二输出位流的DSV控制。
    • 4. 发明授权
    • Computer program for encoding digital data
    • 用于编码数字数据的计算机程序
    • US06686855B2
    • 2004-02-03
    • US10400500
    • 2003-03-28
    • Atsushi HayamiToshio Kuroiwa
    • Atsushi HayamiToshio Kuroiwa
    • H03M700
    • H03M5/145G11B20/1426G11B20/18G11B2020/1457H03M7/46
    • Encoding tables are accorded with variable-length encoding rules using a variable constraint length. A DSV control bit is periodically inserted into a first input bit stream to generate a second input bit stream. Every m-bit piece of the second input bit stream is encoded into an n-bit output signal forming at least a portion of an output code word by referring to the encoding tables. Thereby, the second input bit stream is converted into a first output bit stream composed of output code words and observing RLL (d, k). A sync word is inserted into the first output bit stream for every frame to generate a second output bit stream. A frame-end output code word is terminated at a position before a next-frame sync word. DSV control of the second output bit stream is implemented in response to the inserted DSV control bits.
    • 编码表符合使用可变约束长度的可变长度编码规则。 周期性地将DSV控制位插入到第一输入位流中以产生第二输入位流。 通过参照编码表将第二输入比特流的每个m位片段编码成形成输出码字的至少一部分的n位输出信号。 由此,第二输入比特流被转换成由输出码字组成的第一输出比特流并观察RLL(d,k)。 对于每一帧,将同步字插入到第一输出比特流中以产生第二输出比特流。 帧结束输出码字在下一帧同步字之前的位置终止。 响应于插入的DSV控制位来实现第二输出位流的DSV控制。
    • 9. 发明授权
    • Cryptosystem-related method and apparatus
    • 密码系统相关方法和装置
    • US06891951B2
    • 2005-05-10
    • US09733057
    • 2000-12-11
    • Wataru InohaTakayuki SugaharaToshio KuroiwaKenjiro UedaSeiji Higurashi
    • Wataru InohaTakayuki SugaharaToshio KuroiwaKenjiro UedaSeiji Higurashi
    • H01S3/034H01S3/036H01S3/038H01S3/07H01S3/08H01S3/086H04L9/06H04L9/08H04L9/32H04L9/14
    • H04L9/0618H04L2209/30H04L2209/603
    • Bits of a first bit sequence are rearranged in a first matrix according to a predetermined arrangement rule. The first bit sequence represents information being a base of a key. Blocks are formed in the first matrix. Each of the blocks has bits, the number of which is smaller than the number of bits composing the first matrix. Logical operation is executed among bits in each of the blocks, and a bit being a result of the logical operation is generated. The logical-operation-result bits are combined into a second bit sequence. The number of bits composing the second bit sequence is smaller than the number of bits composing the first bit sequence. There is a second matrix composed of predetermined third bit sequences. The second matrix is accessed and one is read out from among the third bit sequences in response to the second bit sequence. The read-out third bit sequence is outputted as information representative of the key. The number of bits composing each of the third bit sequences is smaller than the number of bits composing the second bit sequence.
    • 根据预定的布置规则,第一比特序列的比特重新排列在第一矩阵中。 第一位序列表示作为键的基础的信息。 块形成在第一矩阵中。 每个块具有位数,其数量小于构成第一矩阵的位数。 在每个块中的位之间执行逻辑运算,并且生成作为逻辑运算结果的位。 逻辑运算结果位被组合成第二位序列。 构成第二比特序列的比特数小于构成第一比特序列的比特数。 存在由预定的第三比特序列组成的第二矩阵。 第二矩阵被访问,并且响应于第二比特序列从第三比特序列中读出一个。 作为代表键的信息输出读出的第3位序列。 构成每个第三比特序列的比特数小于构成第二比特序列的比特数。