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1. 发明授权

US6018786A Trace based instruction caching 失效
标题翻译：基于跟踪的指令缓存
公开(公告)号：US6018786A
公开(公告)日：2000-01-25
申请号：US956375
申请日：1997-10-23
申请人： Robert F. Krick , Glenn J. Hinton , Michael D. Upton , David J. Sager , Chan W. Lee
发明人： Robert F. Krick , Glenn J. Hinton , Michael D. Upton , David J. Sager , Chan W. Lee
IPC分类号： G06F9/32 , G06F9/38 , G06F12/08 , G06F9/26 , G06F12/00
CPC分类号： G06F9/3808 , G06F12/0875 , G06F9/3802 , G06F9/3836
摘要： A cache memory is constituted with a data array and control logic. The data array includes a number of data lines, and the control logic operates to store a number of trace segments of instructions in the data lines, including trace segments that span multiple data lines. In one embodiment, each trace segment includes one or more trace segment members having one or more instructions, with each trace segment member occupying one data line, and the data lines of a multi-line trace segment being sequentially associated (logically). Retrieval of the trace segment members of a multi-line trace segment is accomplished by first locating the data line storing the first trace segment member of the trace segment, and then successively locating the remaining data lines storing the remaining trace segment members based on the data lines' logical sequential associations.
摘要翻译：高速缓冲存储器由数据阵列和控制逻辑构成。数据阵列包括许多数据线，并且控制逻辑操作以在数据线中存储多条迹线段，包括跨越多个数据线的迹线段。在一个实施例中，每个跟踪段包括具有一个或多个指令的一个或多个跟踪段成员，每个跟踪段成员占据一个数据线，并且多行跟踪段的数据线被顺序地相关联（逻辑地）。通过首先定位存储跟踪段的第一跟踪段成员的数据线，然后基于数据连续定位存储剩余跟踪段成员的剩余数据线，来检索多行跟踪段的跟踪段成员行的逻辑顺序关联。

2. 发明授权

US06170038A Trace based instruction caching 有权
标题翻译：基于跟踪的指令缓存
公开(公告)号：US06170038A
公开(公告)日：2001-01-02
申请号：US09447078
申请日：1999-11-22
申请人： Robert F. Krick , Glenn J. Hinton , Michael D. Upton , David J. Sager , Chan W. Lee
发明人： Robert F. Krick , Glenn J. Hinton , Michael D. Upton , David J. Sager , Chan W. Lee
IPC分类号： G06F926
CPC分类号： G06F12/0875
摘要： A cache memory is constituted with a data array and control logic. The data array includes a number of data lines, and the control logic operates to store a number of trace segments of instructions in the data lines, including trace segments that span multiple data lines. In one embodiment, each trace segment includes one or more trace segment members having one or more instructions, with each trace segment member occupying one data line, and the data lines of a multi-line trace segment being sequentially associated (logically). Retrieval of the trace segment members of a multi-line trace segment is accomplished by first locating the data line storing the first trace segment member of the trace segment, and then successively locating the remaining data lines storing the remaining trace segment members based on the data lines' logical sequential associations.
摘要翻译：高速缓冲存储器由数据阵列和控制逻辑构成。数据阵列包括许多数据线，并且控制逻辑操作以在数据线中存储多条迹线段，包括跨越多个数据线的迹线段。在一个实施例中，每个跟踪段包括具有一个或多个指令的一个或多个跟踪段成员，每个跟踪段成员占据一个数据线，并且多行跟踪段的数据线被顺序地相关联（逻辑地）。通过首先定位存储跟踪段的第一跟踪段成员的数据线，然后基于数据连续定位存储剩余跟踪段成员的剩余数据线，来检索多行跟踪段的跟踪段成员行的逻辑顺序关联。

3. 再颁专利

USRE44494E1 Processor having execution core sections operating at different clock rates 有权
公开(公告)号：USRE44494E1
公开(公告)日：2013-09-10
申请号：US10996328
申请日：2004-11-24
申请人： David J. Sager , Thomas D. Fletcher , Glenn J. Hinton , Michael D. Upton
发明人： David J. Sager , Thomas D. Fletcher , Glenn J. Hinton , Michael D. Upton
IPC分类号： G06F1/00 , G06F1/04 , G06F15/00 , G06F15/76 , G06F9/00
CPC分类号： G06F1/02 , G06F1/06 , G06F1/08 , G06F9/30145 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3869 , G06F15/7832
摘要： A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.

4. 发明申请

US20120042151A1 PROCESSOR HAVING EXECUTION CORE SECTIONS OPERATING AT DIFFERENT CLOCK RATES 审中-公开
标题翻译：具有执行核心部分的处理器以不同的时钟速率运行
公开(公告)号：US20120042151A1
公开(公告)日：2012-02-16
申请号：US12879872
申请日：2010-09-10
申请人： David J. Sager , Thomas D. Fletcher , Glenn J. Hinton , Michael D. Upton
发明人： David J. Sager , Thomas D. Fletcher , Glenn J. Hinton , Michael D. Upton
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/3842 , G06F1/08 , G06F9/30145 , G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3863 , G06F9/3869 , G06F15/7832
摘要： A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.
摘要翻译：一种处理器，包括以第一时钟频率执行执行操作的第一执行核心部分和第二执行核心部分，其被计时以在与第一时钟频率不同的第二时钟频率执行执行操作。第二个执行核心部分运行速度更快，包括数据高速缓存和关键的ALU功能，而第一个执行核心部分包括延迟容忍功能，如指令提取和解码单元以及非关键ALU功能。处理器还可以包括可能仍然比第一执行核心部分慢的I / O环。可选地，第一执行核心部分可以包括其时钟速率在第一执行核心部分和第二执行核心部分之间的第三执行核心部分。可以在各部分之间使用时钟乘法器/分频器，以从单个源（例如I / O时钟）导出其时钟。

5. 发明授权

US06256745B1 Processor having execution core sections operating at different clock rates 有权
标题翻译：具有执行核心部分以不同时钟速率工作的处理器
公开(公告)号：US06256745B1
公开(公告)日：2001-07-03
申请号：US09527065
申请日：2000-03-16
申请人： David J. Sager , Thomas D. Fletcher , Glenn J. Hinton , Michael D. Upton
发明人： David J. Sager , Thomas D. Fletcher , Glenn J. Hinton , Michael D. Upton
IPC分类号： G06F106
CPC分类号： G06F1/02 , G06F1/06 , G06F1/08 , G06F9/30145 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3869 , G06F15/7832
摘要： A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.
摘要翻译：一种处理器，包括以第一时钟频率执行执行操作的第一执行核心部分和第二执行核心部分，其被计时以在与第一时钟频率不同的第二时钟频率执行执行操作。第二个执行核心部分运行速度更快，包括数据高速缓存和关键的ALU功能，而第一个执行核心部分包括延迟容忍功能，如指令提取和解码单元以及非关键ALU功能。处理器还可以包括可能比第一执行核心部分慢的I / O环，可选地，第一执行核心部分可以包括其时钟速率在第一和第二执行核心部分之间的时钟速率的第三执行核心部分。可以在各部分之间使用时钟乘法器/分频器，以从单个源（例如I / O时钟）导出其时钟。

6. 发明授权

US06487675B2 Processor having execution core sections operating at different clock rates 有权
标题翻译：具有执行核心部分以不同时钟速率工作的处理器
公开(公告)号：US06487675B2
公开(公告)日：2002-11-26
申请号：US09775383
申请日：2001-02-02
申请人： David J. Sager , Thomas D. Fletcher , Glenn J. Hinton , Michael D. Upton
发明人： David J. Sager , Thomas D. Fletcher , Glenn J. Hinton , Michael D. Upton
IPC分类号： G06F104
CPC分类号： G06F1/02 , G06F1/06 , G06F1/08 , G06F9/30145 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3869 , G06F15/7832
摘要： A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.
摘要翻译：一种处理器，包括以第一时钟频率执行执行操作的第一执行核心部分和第二执行核心部分，其被计时以在与第一时钟频率不同的第二时钟频率执行执行操作。第二个执行核心部分运行速度更快，包括数据高速缓存和关键的ALU功能，而第一个执行核心部分包括延迟容忍功能，如指令提取和解码单元以及非关键ALU功能。处理器还可以包括可能仍然比第一执行核心部分慢的I / O环。可选地，第一执行核心部分可以包括其时钟速率在第一执行核心部分和第二执行核心部分之间的第三执行核心部分。可以在各部分之间使用时钟乘法器/分频器，以从单个源（例如I / O时钟）导出其时钟。

7. 发明授权

US06735688B1 Processor having replay architecture with fast and slow replay paths 有权
标题翻译：具有重放架构的处理器具有快速和慢速的重放路径
公开(公告)号：US06735688B1
公开(公告)日：2004-05-11
申请号：US09503853
申请日：2000-02-14
申请人： Michael D. Upton , David J. Sager , Darrell Boggs , Glenn J. Hinton
发明人： Michael D. Upton , David J. Sager , Darrell Boggs , Glenn J. Hinton
IPC分类号： G06F900
CPC分类号： G06F9/3865 , G06F9/3824 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3869
摘要： According to one aspect of the invention, a microprocessor is provided that includes an execution core, a first replay mechanism and a second replay mechanism. The execution core performs data speculation in executing a first instruction. The first replay mechanism is used to replay the first instruction via a first replay path if an error of a first type is detected which indicates that the data speculation is erroneous. The second replay mechanism is used to replay the first instruction via a second replay path if an error of a second type is detected which indicates that the data speculation is erroneous.
摘要翻译：根据本发明的一个方面，提供一种包括执行核心，第一重放机制和第二重放机构的微处理器。执行核心在执行第一条指令时执行数据推测。如果检测到第一类型的错误，指示数据猜测是错误的，则第一重放机制用于经由第一重放路径重放第一指令。如果检测到第二类型的错误，指示数据猜测是错误的，则第二重播机制用于经由第二重放路径重播第一指令。

8. 发明授权

US06216234B1 Processor having execution core sections operating at different clock rates 失效
标题翻译：具有执行核心部分以不同时钟速率工作的处理器
公开(公告)号：US06216234B1
公开(公告)日：2001-04-10
申请号：US09092353
申请日：1998-06-05
申请人： David J. Sager , Thomas D. Fletcher , Glenn J. Hinton , Michael D. Upton
发明人： David J. Sager , Thomas D. Fletcher , Glenn J. Hinton , Michael D. Upton
IPC分类号： G06F104
CPC分类号： G06F9/3842 , G06F1/08 , G06F9/30145 , G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3863 , G06F9/3869 , G06F15/7832
摘要： A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.
摘要翻译：一种处理器，包括以第一时钟频率执行执行操作的第一执行核心部分和第二执行核心部分，其被计时以在与第一时钟频率不同的第二时钟频率执行执行操作。第二个执行核心部分运行速度更快，包括数据高速缓存和关键的ALU功能，而第一个执行核心部分包括延迟容忍功能，如指令提取和解码单元以及非关键ALU功能。处理器还可以包括可能仍然比第一执行核心部分慢的I / O环。可选地，第一执行核心部分可以包括其时钟速率在第一执行核心部分和第二执行核心部分之间的第三执行核心部分。可以在各部分之间使用时钟乘法器/分频器，以从单个源（例如I / O时钟）导出其时钟。

9. 发明授权

US5828868A Processor having execution core sections operating at different clock rates 失效
公开(公告)号：US5828868A
公开(公告)日：1998-10-27
申请号：US746606
申请日：1996-11-13
申请人： David J. Sager , Thomas D. Fletcher , Glenn J. Hinton , Michael D. Upton
发明人： David J. Sager , Thomas D. Fletcher , Glenn J. Hinton , Michael D. Upton
IPC分类号： G06F1/08 , G06F9/30 , G06F9/38 , G06F15/78 , G06F1/06
CPC分类号： G06F9/3842 , G06F1/08 , G06F15/7832 , G06F9/30145 , G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3863 , G06F9/3869
摘要： A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.

10. 发明授权

US06425055B1 Way-predicting cache memory 有权
标题翻译：预测缓存的方式
公开(公告)号：US06425055B1
公开(公告)日：2002-07-23
申请号：US09256846
申请日：1999-02-24
申请人： David J. Sager , Glenn J. Hinton
发明人： David J. Sager , Glenn J. Hinton
IPC分类号： G06F1200
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： An apparatus and method for accessing a cache memory. In a cache memory, an address is received that includes a set field and a partial tag field, the set field and the partial tag field together including fewer bits than necessary to uniquely identify a region of memory equal in size to a cache line of the cache memory. The set field is decoded to select one of a plurality of storage units within the cache memory, each of the plurality of storage units including a plurality of cache lines of the cache memory. The partial tag field is compared to a plurality of previously stored partial tags that correspond to the plurality of cache lines within the selected one of the plurality of storage units to determine if the partial tag field matches one of the plurality of previously stored partial tags. If the one of the previously stored partial tags matches the partial tag field, one of the plurality of cache lines that corresponds to the one of the plurality of previously stored partial tags is output.
摘要翻译：一种用于访问高速缓冲存储器的装置和方法。在高速缓冲存储器中，接收到包括设置字段和部分标签字段的地址，所述设置字段和部分标签字段一起包括比唯一标识尺寸相等于所述存储器的高速缓存行大小的存储区域所需的位数高速缓存存储器。解码设置字段以选择高速缓冲存储器内的多个存储单元中的一个，多个存储单元中的每一个包括高速缓存存储器的多个高速缓存行。将部分标签字段与多个先前存储的部分标签进行比较，所述部分标签对应于多个存储单元中所选择的一个存储单元内的多个高速缓存行，以确定部分标签字段是否匹配多个先前存储的部分标签之一。如果先前存储的部分标签之一与部分标签字段匹配，则输出与多个先前存储的部分标签之一对应的多条高速缓存行之一。

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