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1. 发明授权

US08390349B1 Sub-picosecond resolution segmented re-circulating stochastic time-to-digital converter 有权
标题翻译：次皮秒分辨率分段重新循环随机时间 - 数字转换器
公开(公告)号：US08390349B1
公开(公告)日：2013-03-05
申请号：US13533341
申请日：2012-06-26
申请人： Ashoke Ravi , Ofir Degani , Hyung Seok Kim , Hasnain Lakdawala , Yee W. Li , Paolo Madoglio
发明人： Ashoke Ravi , Ofir Degani , Hyung Seok Kim , Hasnain Lakdawala , Yee W. Li , Paolo Madoglio
IPC分类号： H03L7/06
CPC分类号： G04F10/005 , H03L2207/50
摘要： Disclosed is a method and apparatus to extend TDC resolution to better than 1 ps without incurring a matching and power penalty. Higher resolution can be achieved by segmenting the resolution between a mismatch free re-circulating time-to-digital converter (RTDC) and a stochastic time-to-digital converter (STDC). The disclosed RTDC replicates the same delay element to eliminate mismatch with the required dynamic range (200 ps for a 5 GHz example) and moderate resolution (3-5 ps typical corresponding to 6-7 bits for the 5 GHz case). While the STDC can achieve a resolution of 50 fs but with a range of only 3-5 ps which also corresponds to approximately 6-7 additional bits by exploiting process variations and mismatch to achieve a very fine resolution with limited dynamic range.
摘要翻译：公开了一种将TDC分辨率提高到1ps而不引起匹配和功率损失的方法和装置。可以通过在不匹配的循环时间数字转换器（RTDC）和随机时间 - 数字转换器（STDC）之间分辨分辨率来实现更高的分辨率。所公开的RTDC复制相同的延迟元件以消除与所需动态范围（对于5GHz示例为200ps）和中等分辨率（3-5ps典型对应于5GHz情况下的6-7位）的失配。虽然STDC可以实现50 fs的分辨率，但只有3-5 ps的范围，这也通过利用过程变化和失配来对应于大约6-7个附加位，以获得有限动态范围的非常精细的分辨率。

2. 发明申请

US20150181643A1 DIRECT DIGITAL FREQUENCY GENERATION USING TIME AND AMPLITUDE 有权
标题翻译：使用时间和幅度的直接数字频率生成
公开(公告)号：US20150181643A1
公开(公告)日：2015-06-25
申请号：US14138508
申请日：2013-12-23
申请人： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Bernd-Ulrich Klepser , Zdravko Boos , Georgios Palaskas , Stefano Pellerano , Paolo Madoglio
发明人： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Bernd-Ulrich Klepser , Zdravko Boos , Georgios Palaskas , Stefano Pellerano , Paolo Madoglio
IPC分类号： H04W88/06 , H04L27/20 , H04B7/06
CPC分类号： H04L7/033 , H03K2005/00234 , H03L7/16 , H04B7/0413 , H04B7/06 , H04L27/152 , H04L27/1525 , H04L27/20 , H04W88/06
摘要： This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.
摘要翻译：本应用程序还讨论了用于在多个无线设备之间共享本地振荡器的装置和方法。在某些示例中，装置可以包括配置成提供具有第一频率的中心振荡器信号的中央频率合成器，第一发射机，第一发射机包括被配置为接收中心振荡器的第一发射数字 - 时间转换器（DTC）并且提供具有第二频率的第一发射机信号和第一接收机，所述第一接收机包括被配置为接收中心振荡器信号并提供具有第一接收频率的第一接收机信号的第一接收DTC。

3. 发明申请

US20130271305A1 RESISTOR-BASED SIGMA-DELTA DAC 有权
标题翻译：基于电阻的SIGMA-DELTA DAC
公开(公告)号：US20130271305A1
公开(公告)日：2013-10-17
申请号：US13995156
申请日：2011-09-30
申请人： Hyung Seok Kim , Yee W. Li , Ashoke Ravi , Hasnain Lakdawala
发明人： Hyung Seok Kim , Yee W. Li , Ashoke Ravi , Hasnain Lakdawala
IPC分类号： H03M3/00 , H03M1/78
CPC分类号： H03M3/50 , G09G3/3688 , H03M1/00 , H03M1/0863 , H03M1/12 , H03M1/747 , H03M1/785 , H03M1/808 , H03M3/30 , H03M3/502
摘要： An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor is coupled to an output node of the resistor-ladder network. An output voltage is generated at the output node that is based on the multi-bit input signal. In one exemplary embodiment, the multi-bit input signal is a sigma-delta (ΣΔ) modulated multi-bit input signal. In another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are related by a binary weighting. In still another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are substantially equal.
摘要翻译：逆变器驱动的电阻梯形数模（DAC）转换器包括一个电阻梯形网络，包括一个多位输入信号的每个位信号的电阻。电阻梯形网络的每个电阻器包括输入端和输出端。每个电阻器的输入端耦合到多位输入信号的对应位信号，并且每个电阻器的输出端耦合到电阻梯形网络的输出节点。在输出节点处产生基于多位输入信号的输出电压。在一个示例性实施例中，多位输入信号是Σ-Δ（SigmaDelta）调制的多位输入信号。在另一示例性实施例中，电阻梯形网络的电阻器的电阻值通过二进制加权相关。在又一示例性实施例中，电阻梯形网络的电阻器的电阻值基本相等。

4. 发明授权

US08941520B2 Resistor-based Σ-ΔDAC 有权
标题翻译：基于电阻和电阻的DAC
公开(公告)号：US08941520B2
公开(公告)日：2015-01-27
申请号：US13995156
申请日：2011-09-30
申请人： Hyung Seok Kim , Yee W. Li , Ashoke Ravi , Hasnain Lakdawala
发明人： Hyung Seok Kim , Yee W. Li , Ashoke Ravi , Hasnain Lakdawala
IPC分类号： H03M3/00 , H03M1/08 , H03M1/80 , H03M1/78 , H03M1/74 , H03M1/00 , H03M1/12 , G09G3/36
CPC分类号： H03M3/50 , G09G3/3688 , H03M1/00 , H03M1/0863 , H03M1/12 , H03M1/747 , H03M1/785 , H03M1/808 , H03M3/30 , H03M3/502
摘要： An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor is coupled to an output node of the resistor-ladder network. An output voltage is generated at the output node that is based on the multi-bit input signal. In one exemplary embodiment, the multi-bit input signal is a sigma-delta (ΣΔ) modulated multi-bit input signal. In another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are related by a binary weighting. In still another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are substantially equal.
摘要翻译：逆变器驱动的电阻梯形数模（DAC）转换器包括一个电阻梯形网络，包括一个多位输入信号的每个位信号的电阻。电阻梯形网络的每个电阻器包括输入端和输出端。每个电阻器的输入端耦合到多位输入信号的对应位信号，并且每个电阻器的输出端耦合到电阻梯形网络的输出节点。在输出节点处产生基于多位输入信号的输出电压。在一个示例性实施例中，多比特输入信号是Σ-Δ（＆Sgr＆amp; Dgr）调制的多位输入信号。在另一示例性实施例中，电阻梯形网络的电阻器的电阻值通过二进制加权相关。在又一示例性实施例中，电阻梯形网络的电阻器的电阻值基本相等。

5. 发明申请

US20150188583A1 FEEDBACK CALIBRATION OF DIGITAL TO TIME CONVERTER 有权
标题翻译：数字到时间转换器的反馈校准
公开(公告)号：US20150188583A1
公开(公告)日：2015-07-02
申请号：US14140801
申请日：2013-12-26
申请人： Ashoke Ravi , Ofir Degani , Hasnain Lakdawala
发明人： Ashoke Ravi , Ofir Degani , Hasnain Lakdawala
IPC分类号： H04B1/04 , H03M1/84
CPC分类号： H04B17/21 , H03F1/3241 , H03M1/1009 , H03M1/82 , H03M1/84 , H04B1/0475 , H04B2001/0425
摘要： This document discusses apparatus and methods for compensating non-linearity of digital-to-time converters (DTCs). In an example, a wireless device can include a digital-to-time converter (DTC) configured to receive a phase data information from a baseband processor and to provide a first modulation signal for generating a wireless signal, a detector configure to receive the first modulation signal and provide an indication of nonlinearities of the DTC, and a pre-distortion module configured to provide pre-distortion information to the DTC using the indication of nonlinearities.
摘要翻译：本文讨论了用于补偿数字到时间转换器（DTC）的非线性的装置和方法。在一个示例中，无线设备可以包括被配置为从基带处理器接收相位数据信息并提供用于生成无线信号的第一调制信号的数字 - 时间转换器（DTC），检测器配置为接收第一调制信号并提供DTC的非线性指示，以及被配置为使用非线性指示向DTC提供预失真信息的预失真模块。

6. 发明申请

US20150116012A1 Digital Voltage Ramp Generator 审中-公开
标题翻译：数字电压斜坡发生器
公开(公告)号：US20150116012A1
公开(公告)日：2015-04-30
申请号：US14066961
申请日：2013-10-30
申请人： Hasnain Lakdawala , Eshel Gordon , Ofir Degani , Ashoke Ravi , Thomas W. Brown
发明人： Hasnain Lakdawala , Eshel Gordon , Ofir Degani , Ashoke Ravi , Thomas W. Brown
IPC分类号： H03K4/12
CPC分类号： H03K4/12 , H03K4/48 , H03K4/502
摘要： According to some embodiments, an all digital ramp generator may use a string of series connected delays or digital to time-based circuits to perform voltage ramp generation. Thus in some embodiments conventional operational amplifier circuits and relaxation oscillators may be replaced for generating triangular ramp waveforms for DC to DC or direct time-based DC to DC converters. The use of delay lines may produce sufficient resolution for many applications. Thus time domain techniques may afford a more digital approach that scales with process technology and allows high speed operation in some embodiments. A design based on use of inverters and capacitors may scale well with process technology. The decoder and drive logic may be integrated into the voltage ramp generation in some embodiments.
摘要翻译：根据一些实施例，全数字斜坡发生器可以使用串联连接的延迟串或数字到基于时间的电路来执行电压斜坡生成。因此，在一些实施例中，常规运算放大器电路和弛豫振荡器可以被替换以产生用于直流到直流或直接基于时间的直流到直流转换器的三角形斜坡波形。使用延迟线可以为许多应用产生足够的分辨率。因此，时域技术可以提供与数字处理技术相比较的数字化方法，并且在一些实施例中允许高速操作。基于逆变器和电容器的设计可以与工艺技术相结合。在一些实施例中，解码器和驱动逻辑可以集成到电压斜坡生成中。

7. 发明申请

US20120142304A1 Power Amplifiers for Wireless Systems 审中-公开
标题翻译：无线系统功率放大器
公开(公告)号：US20120142304A1
公开(公告)日：2012-06-07
申请号：US12958503
申请日：2010-12-02
申请人： Ofir Degani , Ashoke Ravi , Hasnain Lakdawala
发明人： Ofir Degani , Ashoke Ravi , Hasnain Lakdawala
IPC分类号： H04B1/16 , H03F1/00
CPC分类号： H03F1/025 , H03F1/02 , H03F3/19 , H03F3/211 , H03F3/24 , H03F3/245 , H03F2200/102 , H03F2200/507 , H03F2200/511 , H03F2200/516 , H04B2001/045
摘要： A wireless transceiver may include a power amplifier that uses an envelope tracker. The envelope tracker may include stacked buck switching supply modulators, each having two different supply voltages. In one embodiment, the two different supply voltages are higher and lower supply voltages, which relaxes the voltage head room on the switching regulator and allows the use of thin gate fast transistors in some embodiments.
摘要翻译：无线收发器可以包括使用信封跟踪器的功率放大器。包络跟踪器可以包括堆叠的降压开关电源调制器，每个具有两个不同的电源电压。在一个实施例中，两个不同的电源电压是较高和较低的电源电压，其在一些实施例中放宽了开关调节器上的电压头部室并允许使用薄栅极快速晶体管。

8. 发明申请

US20090002086A1 Film bulk acoustic resonator calibration 失效
公开(公告)号：US20090002086A1
公开(公告)日：2009-01-01
申请号：US11823856
申请日：2007-06-28
申请人： Hasnain Lakdawala , Ofir Degani , Ashoke Ravi , Masoud Sajadieh , Soumyanath Krishnamurthy
发明人： Hasnain Lakdawala , Ofir Degani , Ashoke Ravi , Masoud Sajadieh , Soumyanath Krishnamurthy
IPC分类号： H03L1/00
CPC分类号： H03L1/026 , H03L7/1974
摘要： Film bulk acoustic resonators (FBARS) have resonant frequencies that vary with manufacturing variations, but tend to be matched when in proximity on an integrated circuit die. FBAR resonant frequency is determined using a fractional-N synthesizer and comparing phase/frequency of an output signal from the fractional-N synthesizer to a reference. The reference may be derived from a low frequency crystal oscillator, an external signal source, or a communications signal.

9. 发明申请

US20090041108A1 CASCADED PHASE PULSE POSITION AND PULSE WIDTH MODULATION BASED DIGITAL TRANSMITTER 有权
标题翻译：基于脉冲位置和脉冲宽度调制的数字信号发生器
公开(公告)号：US20090041108A1
公开(公告)日：2009-02-12
申请号：US11837043
申请日：2007-08-10
申请人： Ofir Degani , Hasnain Lakdawala , Ashoke Ravi
发明人： Ofir Degani , Hasnain Lakdawala , Ashoke Ravi
IPC分类号： H03K7/10
CPC分类号： H04L25/4902
摘要： Briefly, in accordance with one or more embodiments, a digital transmitter may comprise two or more phase modulators in a cascaded arrangement. The phase modulators may modulate a local oscillator signal using control signals derived from the quadrature baseband data to be transmitted. A closed loop power control feedback arrangement may be used to compare the output power of the transmitter with a desired output signal, and make corrections to the output signal by modifying at least one of the control signals provided to the cascaded phase modulators.
摘要翻译：简而言之，根据一个或多个实施例，数字发射机可以包括两个或更多个级联布置的相位调制器。相位调制器可以使用从要发送的正交基带数据导出的控制信号来调制本地振荡器信号。可以使用闭环功率控制反馈装置来将发射机的输出功率与期望的输出信号进行比较，并且通过修改提供给级联相位调制器的控制信号中的至少一个来对输出信号进行校正。

10. 发明申请

US20090034603A1 SUBRANGING FOR A PULSE POSITION AND PULSE WIDTH MODULATION BASED TRANSMITTER 有权
标题翻译：用于脉冲位置和脉冲宽度调制的发射机的SUBRANGING
公开(公告)号：US20090034603A1
公开(公告)日：2009-02-05
申请号：US12176646
申请日：2008-07-21
申请人： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Itshak Hod , Yorgos Palaskas , Masoud Sajadieh
发明人： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Itshak Hod , Yorgos Palaskas , Masoud Sajadieh
IPC分类号： H03K7/08
CPC分类号： H03K7/10 , H03F3/2178 , H04B1/0483 , H04L25/4902
摘要： Briefly, in accordance with one or more embodiments, in a pulse position and pulse position modulation out-phasing transmitter, the range of the phase angle, theta, may be divided into more than one range to drive a first power amplifier with a first range of theta, and to drive a second power amplifier with a second range of theta. In one or more embodiments, a main power amplifier is driven with a first phase range having a higher probability density function, and an overload power amplifier is driven with a first phase range having a lower probability density function. In one or more embodiments, a full adder may be used to combine the two phases wherein the sum signal is used to drive the main power amplifier, and the carry signal is used to drive the overload power amplifier.
摘要翻译：简而言之，根据一个或多个实施例，在脉冲位置和脉冲位置调制输出相位变送器中，相位角θ的范围可被划分成多于一个范围以驱动具有第一范围的第一功率放大器的θ，并驱动具有θ的第二范围的第二功率放大器。在一个或多个实施例中，主功率放大器由具有较高概率密度函数的第一相位范围驱动，而过载功率放大器由具有较低概率密度函数的第一相位范围驱动。在一个或多个实施例中，全加器可以用于组合两相，其中求和信号用于驱动主功率放大器，并且进位信号用于驱动过载功率放大器。

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