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1. 发明授权

US08638120B2 Programmable gate array as drivers for data ports of spare latches 有权
标题翻译：可编程门阵列作为备用锁存器数据端口的驱动器
公开(公告)号：US08638120B2
公开(公告)日：2014-01-28
申请号：US13246037
申请日：2011-09-27
申请人： Ashish Jaitly , Sridhar H. Rangarajan , Thomas E. Rosser
发明人： Ashish Jaitly , Sridhar H. Rangarajan , Thomas E. Rosser
IPC分类号： G06F7/38
CPC分类号： H03K19/17744 , G06F17/5054 , G06F2217/72
摘要： Aspects of the invention provide for improving a success rate of an engineering design change (ECO) for an integrated circuit. In one embodiment, aspects of the invention include a method for improving a success rate of an engineering design change (ECO) for an integrated circuit, including: identifying a plurality of spare latches within the integrated circuit; determining an input driver for each of the spare latches; and replacing each input driver with a programmable gate array, such that the programmable gate array is programmed to a functionality of the input driver.
摘要翻译：本发明的方面提供了用于提高集成电路的工程设计变更（ECO）的成功率。在一个实施例中，本发明的方面包括用于提高集成电路的工程设计变更（ECO）的成功率的方法，包括：识别集成电路内的多个备用锁存器; 确定每个备用锁存器的输入驱动器; 并且用可编程门阵列替换每个输入驱动器，使得可编程门阵列被编程为输入驱动器的功能。

2. 发明申请

US20130076391A1 PROGRAMMABLE GATE ARRAY AS DRIVERS FOR DATA PORTS OF SPARE LATCHES 有权
标题翻译：可编程门阵列作为备用锁存器数据端口的驱动器
公开(公告)号：US20130076391A1
公开(公告)日：2013-03-28
申请号：US13246037
申请日：2011-09-27
申请人： Ashish Jaitly , Sridhar H. Rangarajan , Thomas E. Rosser
发明人： Ashish Jaitly , Sridhar H. Rangarajan , Thomas E. Rosser
IPC分类号： H03K19/177 , G06F17/50
CPC分类号： H03K19/17744 , G06F17/5054 , G06F2217/72
摘要： Aspects of the invention provide for improving a success rate of an engineering design change (ECO) for an integrated circuit. In one embodiment, aspects of the invention include a method for improving a success rate of an engineering design change (ECO) for an integrated circuit, including: identifying a plurality of spare latches within the integrated circuit; determining an input driver for each of the spare latches; and replacing each input driver with a programmable gate array, such that the programmable gate array is programmed to a functionality of the input driver.
摘要翻译：本发明的方面提供了用于提高集成电路的工程设计变更（ECO）的成功率。在一个实施例中，本发明的方面包括一种用于提高集成电路的工程设计变更（ECO）的成功率的方法，包括：识别集成电路内的多个备用锁存器; 确定每个备用锁存器的输入驱动器; 并且用可编程门阵列替换每个输入驱动器，使得可编程门阵列被编程为输入驱动器的功能。

3. 发明授权

US08572536B2 Spare latch distribution 失效
标题翻译：备用锁存器分配
公开(公告)号：US08572536B2
公开(公告)日：2013-10-29
申请号：US13246038
申请日：2011-09-27
申请人： George Antony , Sridhar H. Rangarajan , Thomas E. Rosser
发明人： George Antony , Sridhar H. Rangarajan , Thomas E. Rosser
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/72
摘要： Aspects of the invention provide for spare latch distribution for an integrated circuit design. In one embodiment, aspects of the invention include a method of generating a computer system for spare latch distribution in an integration circuit design, the method including: providing a computer system operable to: receive design data for the integrated circuit design, the design data including a plurality of latches; segment the integrated circuit design into a plurality of equal sections; determine a latch density within each of the equal sections; and determine a number of spare latches, based on the latch density, for each of the equal sections. Further, it is understood that the above are performed for each clock domain within the integrated circuit design.
摘要翻译：本发明的方面提供用于集成电路设计的备用锁存器分配。在一个实施例中，本发明的方面包括在集成电路设计中产生用于备用锁存器分配的计算机系统的方法，所述方法包括：提供计算机系统，其可操作以：接收所述集成电路设计的设计数据，所述设计数据包括多个闩锁; 将集成电路设计分段成多个相等的部分; 确定每个相等部分内的锁存密度; 并且基于每个相等部分的锁存密度来确定多个备用锁存器。此外，应当理解，在集成电路设计中对于每个时钟域执行上述操作。

4. 发明申请

US20130080989A1 SPARE LATCH DISTRIBUTION 失效
标题翻译：备用分配
公开(公告)号：US20130080989A1
公开(公告)日：2013-03-28
申请号：US13246038
申请日：2011-09-27
申请人： George Antony , Sridhar H. Rangarajan , Thomas E. Rosser
发明人： George Antony , Sridhar H. Rangarajan , Thomas E. Rosser
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/72
摘要： Aspects of the invention provide for spare latch distribution for an integrated circuit design. In one embodiment, aspects of the invention include a method of generating a computer system for spare latch distribution in an integration circuit design, the method including: providing a computer system operable to: receive design data for the integrated circuit design, the design data including a plurality of latches; segment the integrated circuit design into a plurality of equal sections; determine a latch density within each of the equal sections; and determine a number of spare latches, based on the latch density, for each of the equal sections. Further, it is understood that the above are performed for each clock domain within the integrated circuit design.
摘要翻译：本发明的方面提供用于集成电路设计的备用锁存器分配。在一个实施例中，本发明的方面包括在集成电路设计中产生用于备用锁存器分配的计算机系统的方法，所述方法包括：提供计算机系统，其可操作以：接收所述集成电路设计的设计数据，所述设计数据包括多个闩锁; 将集成电路设计分段成多个相等的部分; 确定每个相等部分内的锁存密度; 并且基于每个相等部分的锁存密度来确定多个备用锁存器。此外，应当理解，在集成电路设计中对于每个时钟域执行上述操作。

5. 发明申请

US20130152028A1 NATIVE THRESHOLD VOLTAGE SWITCHING 有权
标题翻译：电压门限开关
公开(公告)号：US20130152028A1
公开(公告)日：2013-06-13
申请号：US13315406
申请日：2011-12-09
申请人： George Antony , Sridhar H. Rangarajan , Alexander J. Suess
发明人： George Antony , Sridhar H. Rangarajan , Alexander J. Suess
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068 , G06F2217/78
摘要： A computer-implemented method of determining threshold voltage levels within a macro of integrated circuit cells. In one embodiment, the method includes: referencing a library of the integrated circuit cells in the macro; estimating a leakage power and a dynamic power for a first integrated circuit cell in the macro; comparing the leakage power with the dynamic power; switching the first integrated circuit cell to a low threshold voltage level in response to determining the dynamic power is greater than the leakage power; and updating the library with a voltage level of the first integrated circuit cell.
摘要翻译：一种确定集成电路单元宏块内的阈值电压电平的计算机实现的方法。在一个实施例中，该方法包括：参考宏中的集成电路单元的库; 估计宏中的第一集成电路单元的泄漏功率和动态功率; 将泄漏功率与动力功率进行比较; 响应于确定动态功率而将第一集成电路单元切换到低阈值电压电平大于泄漏功率; 以及用第一集成电路单元的电压电平更新库。

6. 发明授权

US08495553B2 Native threshold voltage switching 有权
标题翻译：本机阈值电压切换
公开(公告)号：US08495553B2
公开(公告)日：2013-07-23
申请号：US13315406
申请日：2011-12-09
申请人： George Antony , Sridhar H. Rangarajan , Alexander J. Suess
发明人： George Antony , Sridhar H. Rangarajan , Alexander J. Suess
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068 , G06F2217/78
摘要： A computer-implemented method of determining threshold voltage levels within a macro of integrated circuit cells. In one embodiment, the method includes: referencing a library of the integrated circuit cells in the macro; estimating a leakage power and a dynamic power for a first integrated circuit cell in the macro; comparing the leakage power with the dynamic power; switching the first integrated circuit cell to a low threshold voltage level in response to determining the dynamic power is greater than the leakage power; and updating the library with a voltage level of the first integrated circuit cell.
摘要翻译：一种确定集成电路单元宏块内的阈值电压电平的计算机实现的方法。在一个实施例中，该方法包括：参考宏中的集成电路单元的库; 估计宏中的第一集成电路单元的泄漏功率和动态功率; 将泄漏功率与动力功率进行比较; 响应于确定动态功率而将第一集成电路单元切换到低阈值电压电平大于泄漏功率; 以及用第一集成电路单元的电压电平更新库。

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