专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08156409B2 Selectively applied hybrid min-sum approximation for constraint node updates of LDPC decoders 有权
标题翻译：对LDPC解码器的约束节点更新进行选择性应用的混合最小和近似
公开(公告)号：US08156409B2
公开(公告)日：2012-04-10
申请号：US12040230
申请日：2008-02-29
申请人： Ara Patapoutian , Rose Y. Shao , Arvind Sridharan
发明人： Ara Patapoutian , Rose Y. Shao , Arvind Sridharan
IPC分类号： H03M13/00
CPC分类号： H03M13/112 , H03M13/3707 , H03M13/6502 , H03M13/6583
摘要： In accordance with one or more embodiments, a decoder may determine whether a lowest reliability value of a plurality of codeword bits that correspond to a particular output reliability value for a particular constraint node of a parity-check matrix is greater than a threshold value (e.g., an offset), and if so, selectively applies a modified min-sum approximation constraint node update with a reliability value modification (e.g., an offset or normalized min-sum approximation).
摘要翻译：根据一个或多个实施例，解码器可以确定对应于奇偶校验矩阵的特定约束节点的特定输出可靠性值的多个码字比特的最低可靠性值是否大于阈值（例如，，偏移），如果是，则选择性地应用具有可靠性值修改（例如，偏移或归一化最小和近似）的经修改的最小和近似约束节点更新。

2. 发明授权

US07752531B2 Defect sensing Viterbi based detector 有权
标题翻译：缺陷检测维特比检测器
公开(公告)号：US07752531B2
公开(公告)日：2010-07-06
申请号：US11854214
申请日：2007-09-12
申请人： Ara Patapoutian , Rose Y. Shao
发明人： Ara Patapoutian , Rose Y. Shao
IPC分类号： H03M13/03
CPC分类号： H03M13/3738 , H03M13/1102 , H03M13/2957 , H03M13/373 , H03M13/4146
摘要： A detector includes a Viterbi based detector and an erasure detector that detects as erasures one or more bits associated with a decoding window in which survivor paths do not merge within the decoding window.
摘要翻译：检测器包括基于维特比的检测器和擦除检测器，该检测器检测作为擦除与解码窗口相关联的一个或多个位，其中幸存路径在解码窗口内不合并。

3. 发明申请

US20090070658A1 DEFECT SENSING VITERBI BASED DETECTOR 有权
标题翻译：缺陷感知基于VITERBI的检测器
公开(公告)号：US20090070658A1
公开(公告)日：2009-03-12
申请号：US11854214
申请日：2007-09-12
申请人： Ara Patapoutian , Rose Y Shao
发明人： Ara Patapoutian , Rose Y Shao
IPC分类号： H03M13/03 , G06F11/08
CPC分类号： H03M13/3738 , H03M13/1102 , H03M13/2957 , H03M13/373 , H03M13/4146
摘要： During decoding using a Viterbi based detector, erasures are detected when surviving paths do not merge in an associated decoding window.
摘要翻译：在使用基于维特比的检测器的解码期间，当存活路径不在相关联的解码窗口中合并时，检测到擦除。

4. 发明申请

US20090222710A1 SELECTIVELY APPLIED HYBRID MIN-SUM APPROXIMATION FOR CONSTRAINT NODE UPDATES OF LDPC DECODERS 有权
标题翻译： LDPC解码器的约束节点更新的选择性混合最小最小似然估计
公开(公告)号：US20090222710A1
公开(公告)日：2009-09-03
申请号：US12040230
申请日：2008-02-29
申请人： Ara Patapoutian , Rose Y. Shao , Arvind Sridharan
发明人： Ara Patapoutian , Rose Y. Shao , Arvind Sridharan
IPC分类号： H03M13/00
CPC分类号： H03M13/112 , H03M13/3707 , H03M13/6502 , H03M13/6583
摘要： In accordance with one or more embodiments, a decoder may determine whether a lowest reliability value of a plurality of codeword bits that correspond to a particular output reliability value for a particular constraint node of a parity-check matrix is greater than a threshold value (e.g., an offset), and if so, selectively applies a modified min-sum approximation constraint node update with a reliability value modification (e.g., an offset or normalized min-sum approximation).
摘要翻译：根据一个或多个实施例，解码器可以确定对应于奇偶校验矩阵的特定约束节点的特定输出可靠性值的多个码字比特的最低可靠性值是否大于阈值（例如，，偏移），如果是，则选择性地应用具有可靠性值修改（例如，偏移或归一化最小和近似）的经修改的最小和近似约束节点更新。

5. 发明申请

US20170041099A1 Multiuse Data Channel 审中-公开
标题翻译：多用数据通道
公开(公告)号：US20170041099A1
公开(公告)日：2017-02-09
申请号：US14820137
申请日：2015-08-06
申请人： Ara Patapoutian , Hieu V. Nguyen
发明人： Ara Patapoutian , Hieu V. Nguyen
IPC分类号： H04L1/00 , H03M13/11 , G11C29/52 , H03M13/29 , G06F11/10
CPC分类号： H04L1/0045 , G06F11/1072 , G11C29/52 , H03M13/09 , H03M13/1102 , H03M13/1515 , H03M13/2906 , H03M13/6516 , H03M13/6561
摘要： Presented is a data channel with selectable components, such as encoders or decoders. Also, data having different data signal characteristics can be processed through a data channel based on the data signal characteristics. Further, a data channel may have independent encoding path and an independent decoding path. For example, a first data transmission having first data signal characteristics may be processed via a data channel based on a first selected set of components of the data channel and a second data transmission having second data signal characteristics different than the first data signal characteristics may be processed via the data channel using a second selected set of components in the data channel. The first selected set of components may be different than the second selected set of components, but may share one or more common components.
摘要翻译：提出了具有可选组件的数据通道，例如编码器或解码器。此外，可以基于数据信号特性通过数据信道来处理具有不同数据信号特性的数据。此外，数据信道可以具有独立的编码路径和独立的解码路径。例如，具有第一数据信号特性的第一数据传输可以经由数据信道基于数据信道的第一选定组件集合进行处理，并且具有与第一数据信号特性不同的第二数据信号特性的第二数据传输可以是通过数据信道使用数据信道中的第二组选择的组来处理。第一选择的组件集合可以不同于第二选择的组件集合，但是可以共享一个或多个公共组件。

6. 发明授权

US09473266B1 Scheduling strategies for iterative decoders 有权
标题翻译：迭代解码器的调度策略
公开(公告)号：US09473266B1
公开(公告)日：2016-10-18
申请号：US12473728
申请日：2009-05-28
申请人： Ara Patapoutian , Bruce Buch , Rose Shao
发明人： Ara Patapoutian , Bruce Buch , Rose Shao
IPC分类号： G06F11/00 , H04L1/00
CPC分类号： H03M13/1111 , H03M13/1105 , H03M13/3738 , H03M13/3746 , H03M13/3784 , H03M13/616 , H03M13/6325 , H04L1/0057
摘要： An iterative decoder is controlled to iteratively decode a block by performing one or more decoding iterations for the block. The iterative decoder uses a parity-check matrix and can be configured to process that parity-check matrix for parallel, sequential or a combination of parallel and sequential (“hybrid”) parity constraint updates.
摘要翻译：控制迭代解码器以通过对该块执行一个或多个解码迭代来迭代地解码块。迭代解码器使用奇偶校验矩阵，并且可以被配置为处理用于并行，顺序或并行和顺序（“混合”）奇偶校验约束更新的组合的奇偶校验矩阵。

7. 发明授权

US08760986B2 Read channel throughput management 有权
标题翻译：读取通道吞吐量管理
公开(公告)号：US08760986B2
公开(公告)日：2014-06-24
申请号：US13408849
申请日：2012-02-29
申请人： Prafulla Bollampalli Reddy , Hui Su , Michelle Elaine Blankenship , Eddie Wai Pun , John Marc Wright , Ara Patapoutian , Hieu V Nguyen
发明人： Prafulla Bollampalli Reddy , Hui Su , Michelle Elaine Blankenship , Eddie Wai Pun , John Marc Wright , Ara Patapoutian , Hieu V Nguyen
IPC分类号： G11B11/00
CPC分类号： G11B20/1217 , G11B5/09 , G11B20/10527 , G11B20/1833 , G11B2020/10759 , G11B2020/10916 , G11B2020/1232 , G11B2020/1295 , G11B2020/185
摘要： An implementation of a system disclosed herein provides a method of deferring decoding of a data sector received at a read channel of a storage device, in response to determining that a data sector cannot be decoded by a first decoder and storing the data sector for further processing by a second decoder.
摘要翻译：响应于确定数据扇区不能由第一解码器解码并存储数据扇区用于进一步处理的方法，本文公开的系统的实现提供了一种在存储设备的读取信道上推迟对数据扇区进行解码的方法通过第二解码器。

8. 发明授权

US08627175B2 Opportunistic decoding in memory systems 有权
标题翻译：内存系统中的机会解码
公开(公告)号：US08627175B2
公开(公告)日：2014-01-07
申请号：US12891490
申请日：2010-09-27
申请人： Ara Patapoutian , Bernardo Rub , Bruce D. Buch
发明人： Ara Patapoutian , Bernardo Rub , Bruce D. Buch
IPC分类号： G11C29/00
CPC分类号： G06F11/1008 , G06F11/1048 , G11C16/26 , G11C29/844 , H03M13/1108 , H03M13/1111 , H03M13/3707 , H03M13/45 , H03M13/451 , H03M13/458
摘要： Approaches for decoding data read from memory cells of a nonvolatile, solid state memory involve attempting to decode hard data using a hard decoding process prior to a time that soft data is available to the decoder. The hard data includes information about the digital symbols stored in the memory cells without data confidence information. The soft data includes information about the digital symbols stored in the memory cells and data confidence information. In response to the hard decoding process failing to achieve convergence, after the soft data becomes available to the decoder, the soft data is decoded using a soft decoding process. The decoder generates an output of the decoded data after the hard decoding process or the soft decoding process achieves convergence.
摘要翻译：用于解码从非易失性固态存储器的存储器单元读取的数据的方法包括在软数据可用于解码器的时间之前尝试使用硬解码处理对硬数据进行解码。硬数据包括关于存储在存储器单元中的数字符号的信息，而没有数据置信度信息。软数据包括关于存储在存储单元中的数字符号和数据置信度的信息。响应于难以实现收敛的硬解码处理，在软数据变得可用于解码器之后，使用软解码处理解码软数据。在硬解码处理或软解码处理实现收敛之后，解码器生成解码数据的输出。

9. 发明申请

US20110296272A1 OUTER CODE PROTECTION FOR SOLID STATE MEMORY DEVICES 有权
标题翻译：固态存储器件的外部代码保护
公开(公告)号：US20110296272A1
公开(公告)日：2011-12-01
申请号：US12790120
申请日：2010-05-28
申请人： Bernardo Rub , Ara Patapoutian , Arvind Sridharan , Bruce D. Buch
发明人： Bernardo Rub , Ara Patapoutian , Arvind Sridharan , Bruce D. Buch
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： G06F11/1012
摘要： Outer code words can span multiple data blocks, multiple die, or multiple chips of a memory device to protect against errors in the data stored in the blocks, die and/or chips. A solid state memory device is arranged in multiple data blocks, each block including an array of memory cells arranged in a plurality of pages. The data is encoded into inner code words and symbol-based outer code words. The inner code words and the symbol-based outer code words are stored in the memory cells of the multiple blocks. One or more inner code words are stored in each page of each block and one or more symbols of each outer code word are stored in at least one page of each block. The inner code words and the outer code words are read from the memory device and are used to correct the errors in the data.
摘要翻译：外码字可以跨越存储器设备的多个数据块，多个芯片或多个芯片，以防止存储在块，芯片和/或芯片中的数据中的错误。固态存储器件被布置在多个数据块中，每个块包括以多页布置的存储器单元的阵列。数据被编码成内码字和基于符号的外码字。内码字和基于符号的外码字被存储在多个块的存储单元中。一个或多个内部码字被存储在每个块的每个页面中，并且每个外部码字的一个或多个符号被存储在每个块的至少一个页面中。内部码字和外部码字从存储器件读取并用于校正数据中的错误。

10. 发明授权

US08040994B1 Phase coefficient generation for PLL 有权
标题翻译： PLL的相位系数生成
公开(公告)号：US08040994B1
公开(公告)日：2011-10-18
申请号：US11688063
申请日：2007-03-19
申请人： Ara Patapoutian
发明人： Ara Patapoutian
IPC分类号： H03D3/24
CPC分类号： H03L7/1075
摘要： A method and apparatus is provided for synchronizing a clock signal by generating time varying PLL phase coefficients which approximate optimal PLL phase coefficients. An acquisition mode phase coefficient is determined by adding an error signal (A) to the sample counter (k) and finding the reciprocal of the result (1/(A+k)). The reciprocal can be calculated in hardware or determined by using a lookup table. A tracking mode phase coefficient is determined based on the error signal for use in the PLL during a track a tracking period. The tracking period begins when the tracking mode coefficient is greater than the acquisition mode coefficient.
摘要翻译：提供了一种通过产生近似最佳PLL相位系数的时变PLL相位系数来同步时钟信号的方法和装置。通过将采样计数器（k）的误差信号（A）相加并求出结果的倒数（1 /（A + k））来确定采集模式相位系数。可以用硬件计算倒数或使用查找表确定倒数。基于在跟踪期间的轨道期间在PLL中使用的误差信号来确定跟踪模式相位系数。当跟踪模式系数大于采集模式系数时，跟踪周期开始。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式