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1. 发明申请

US20130275829A1 USING A SOFT DECODER WITH HARD DATA 有权
标题翻译：使用硬数据的软解码器
公开(公告)号：US20130275829A1
公开(公告)日：2013-10-17
申请号：US13445591
申请日：2012-04-12
申请人： Deepak Sridhara , Arvind Sridharan , Ara Patapoutian
发明人： Deepak Sridhara , Arvind Sridharan , Ara Patapoutian
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： G06F11/1048 , G11C11/5642 , H03M13/1111 , H03M13/2957 , H03M13/3707 , H03M13/6325 , H03M13/6511 , H03M13/6577
摘要： A method for re-using a soft decoder involves receiving soft data and hard data from memory cells in a memory device, mapping the soft data to a first set of soft information, mapping the hard data to a second set of soft information, and using the soft decoder to decode both the first set and second set of soft information.
摘要翻译：用于重新使用软解码器的方法包括从存储器设备中的存储器单元接收软数据和硬数据，将软数据映射到第一组软信息，将硬数据映射到第二组软信息，并使用软解码器解码第一组和第二组软信息。

2. 发明申请

US20130094289A1 DETERMINATION OF MEMORY READ REFERENCE AND PROGRAMMING VOLTAGES 有权
标题翻译：记忆读取参考和编程电压的确定
公开(公告)号：US20130094289A1
公开(公告)日：2013-04-18
申请号：US13275497
申请日：2011-10-18
申请人： Arvind Sridharan , Ara Patapoutian
发明人： Arvind Sridharan , Ara Patapoutian
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/28 , G11C16/3418
摘要： Symmetrical or asymmetrical noise distributions for voltages corresponding to symbols that can be stored in multi-level memory cells (MLCs) of a memory device are used to determine read reference and/or programming voltages. The read reference voltages and/or programming voltages for the MLCs are jointly determined using the symmetrical distributions and a maximum likelihood estimation (MLE) and/or by determining at least one of the read reference voltages and the programming voltages using the asymmetrical distributions.
摘要翻译：用于对应于可存储在存储器件的多级存储器单元（MLC）中的符号的电压的对称或非对称噪声分布用于确定读取参考和/或编程电压。使用对称分布和最大似然估计（MLE）和/或通过使用不对称分布确定读取的参考电压和编程电压中的至少一个来共同确定MLC的读取参考电压和/或编程电压。

3. 发明申请

US20130094286A1 DETERMINING OPTIMAL READ REFERENCE AND PROGRAMMING VOLTAGES FOR NON-VOLATILE MEMORY USING MUTUAL INFORMATION 失效
标题翻译：使用相关信息确定非易失性存储器的最佳读取参考和编程电压
公开(公告)号：US20130094286A1
公开(公告)日：2013-04-18
申请号：US13275598
申请日：2011-10-18
申请人： Arvind Sridharan , Ara Patapoutian
发明人： Arvind Sridharan , Ara Patapoutian
IPC分类号： G11C16/10
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3418
摘要： Approaches for operating a memory device comprising memory cells are disclosed. Optimal values for one or more of programming voltages used to program memory cells of the memory device and read reference voltages used to read the memory cells are determined using a mutual information function, I(X; Y), where X represents data values programmed to the memory cells and Y represents data values read from the memory cells. The read reference and/or programming voltages used for reading and/or programming the memory cells are adjusted using the optimal values.
摘要翻译：公开了用于操作包括存储器单元的存储器件的方法。使用用于对存储器件的存储器单元编程的一个或多个编程电压和用于读取存储器单元的读取参考电压的最佳值使用互信息函数I（X; Y）确定，其中X表示被编程为存储单元，Y表示从存储器单元读取的数据值。用于读取和/或编程存储器单元的读取参考和/或编程电压使用最佳值进行调整。

4. 发明申请

US20110296272A1 OUTER CODE PROTECTION FOR SOLID STATE MEMORY DEVICES 有权
标题翻译：固态存储器件的外部代码保护
公开(公告)号：US20110296272A1
公开(公告)日：2011-12-01
申请号：US12790120
申请日：2010-05-28
申请人： Bernardo Rub , Ara Patapoutian , Arvind Sridharan , Bruce D. Buch
发明人： Bernardo Rub , Ara Patapoutian , Arvind Sridharan , Bruce D. Buch
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： G06F11/1012
摘要： Outer code words can span multiple data blocks, multiple die, or multiple chips of a memory device to protect against errors in the data stored in the blocks, die and/or chips. A solid state memory device is arranged in multiple data blocks, each block including an array of memory cells arranged in a plurality of pages. The data is encoded into inner code words and symbol-based outer code words. The inner code words and the symbol-based outer code words are stored in the memory cells of the multiple blocks. One or more inner code words are stored in each page of each block and one or more symbols of each outer code word are stored in at least one page of each block. The inner code words and the outer code words are read from the memory device and are used to correct the errors in the data.
摘要翻译：外码字可以跨越存储器设备的多个数据块，多个芯片或多个芯片，以防止存储在块，芯片和/或芯片中的数据中的错误。固态存储器件被布置在多个数据块中，每个块包括以多页布置的存储器单元的阵列。数据被编码成内码字和基于符号的外码字。内码字和基于符号的外码字被存储在多个块的存储单元中。一个或多个内部码字被存储在每个块的每个页面中，并且每个外部码字的一个或多个符号被存储在每个块的至少一个页面中。内部码字和外部码字从存储器件读取并用于校正数据中的错误。

5. 发明授权

US09015549B2 Iterating inner and outer codes for data recovery 有权
标题翻译：迭代内部和外部代码进行数据恢复
公开(公告)号：US09015549B2
公开(公告)日：2015-04-21
申请号：US13094048
申请日：2011-04-26
申请人： Bernardo Rub , Ara Patapoutian , Arvind Sridharan , Bruce D. Buch
发明人： Bernardo Rub , Ara Patapoutian , Arvind Sridharan , Bruce D. Buch
IPC分类号： H03M13/00 , G11B20/18 , H03M13/29 , H03M13/37 , H03M13/11 , H03M13/15
CPC分类号： G11B20/1833 , G11B2020/1836 , G11B2020/1853 , G11B2220/2516 , H03M13/1102 , H03M13/1515 , H03M13/2909 , H03M13/2927 , H03M13/3746
摘要： A storage medium includes at least one data unit defining a plurality of symbol-based inner code words and a plurality of symbol-based outer code words. Each symbol included in one of the inner code words is also included in one of the outer code words. A processor is configured to perform a first iteration of inner code error correction on the plurality of symbol-based inner code words, a first iteration of outer code error correction on the plurality of symbol-based outer code words and a second iteration of inner code error correction on the plurality of symbol-based inner code words. In the first iteration of outer code error corrections, at least one of the outer code words is correctable. In the second iteration of inner code error correction, at least one of the inner code words is correctable.
摘要翻译：存储介质包括定义多个基于符号的内码字和多个基于符号的外码字的至少一个数据单元。包含在其中一个内部码字中的每个符号也被包括在一个外部码字中。处理器被配置为对所述多个基于符号的内码字执行内码纠错的第一迭代，对所述多个基于符号的外码字进行外码纠错的第一迭代和内码的第二次迭代对多个基于符号的内码字进行纠错。在外码错误校正的第一次迭代中，外码字中的至少一个是可校正的。在内码纠错的第二次迭代中，内码字中的至少一个是可校正的。

6. 发明授权

US08943384B2 Using a soft decoder with hard data 有权
标题翻译：使用具有硬数据的软解码器
公开(公告)号：US08943384B2
公开(公告)日：2015-01-27
申请号：US13445591
申请日：2012-04-12
申请人： Deepak Sridhara , Arvind Sridharan , Ara Patapoutian
发明人： Deepak Sridhara , Arvind Sridharan , Ara Patapoutian
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： G06F11/1048 , G11C11/5642 , H03M13/1111 , H03M13/2957 , H03M13/3707 , H03M13/6325 , H03M13/6511 , H03M13/6577
摘要： A method for re-using a soft decoder involves receiving soft data and hard data from memory cells in a memory device, mapping the soft data to a first set of soft information, mapping the hard data to a second set of soft information, and using the soft decoder to decode both the first set and second set of soft information.
摘要翻译：用于重新使用软解码器的方法包括从存储器设备中的存储器单元接收软数据和硬数据，将软数据映射到第一组软信息，将硬数据映射到第二组软信息，并使用软解码器解码第一组和第二组软信息。

7. 发明授权

US08693257B2 Determining optimal read reference and programming voltages for non-volatile memory using mutual information 失效
标题翻译：使用相互信息确定非易失性存储器的最佳读取参考和编程电压
公开(公告)号：US08693257B2
公开(公告)日：2014-04-08
申请号：US13275598
申请日：2011-10-18
申请人： Arvind Sridharan , Ara Patapoutian
发明人： Arvind Sridharan , Ara Patapoutian
IPC分类号： G11C16/10
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3418
摘要： Approaches for operating a memory device comprising memory cells are disclosed. Optimal values for one or more of programming voltages used to program memory cells of the memory device and read reference voltages used to read the memory cells are determined using a mutual information function, I(X; Y), where X represents data values programmed to the memory cells and Y represents data values read from the memory cells. The read reference and/or programming voltages used for reading and/or programming the memory cells are adjusted using the optimal values.
摘要翻译：公开了用于操作包括存储器单元的存储器件的方法。使用用于对存储器件的存储器单元编程的一个或多个编程电压和用于读取存储器单元的读取参考电压的最佳值使用互信息函数I（X; Y）确定，其中X表示被编程为存储单元，Y表示从存储器单元读取的数据值。用于读取和/或编程存储器单元的读取参考和/或编程电压使用最佳值进行调整。

8. 发明申请

US20130094290A1 SHIFTING CELL VOLTAGE BASED ON GROUPING OF SOLID-STATE, NON-VOLATILE MEMORY CELLS 有权
标题翻译：基于固态，非易失性存储器电池的分组转换电池电压
公开(公告)号：US20130094290A1
公开(公告)日：2013-04-18
申请号：US13275675
申请日：2011-10-18
申请人： Arvind Sridharan , Ara Patapoutian
发明人： Arvind Sridharan , Ara Patapoutian
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/06 , G11C16/28 , G11C16/349 , G11C29/00
摘要： Cells of a solid-state, non-volatile memory are assigned to one of a plurality of groups. Each group is defined by expected symbols stored in the cells in view of actual symbols read from the cells. Based on cell counts within the groups, it can be determined that a shift in a reference voltage will reduce a collective bit error rate of the cells. The shift can be applied to data access operations affecting the cells.
摘要翻译：将固态非易失性存储器的单元分配给多个组中的一个。鉴于从单元读取的实际符号，每个组由存储在单元中的预期符号定义。基于组内的单元计数，可以确定参考电压的偏移将降低单元的集合误码率。该移位可以应用于影响单元的数据访问操作。

9. 发明授权

US08166364B2 Low density parity check decoder using multiple variable node degree distribution codes 有权
标题翻译：低密度奇偶校验解码器使用多个可变节点度分布码
公开(公告)号：US08166364B2
公开(公告)日：2012-04-24
申请号：US12185437
申请日：2008-08-04
申请人： Ara Patapoutian , Arvind Sridharan
发明人： Ara Patapoutian , Arvind Sridharan
IPC分类号： G06F11/00
CPC分类号： H03M13/1111 , H03M13/2957 , H03M13/3707 , H03M13/6343
摘要： A decoding system comprises an iterative decoder that utilizes parity constraints to iteratively decode a block of data that consists of multiple code words, and a processor that controls the iterative decoder to selectively remove a subset of the parity constraints for a number of decoder iterations and include one or more of the selectively removed parity constraints in other decoder iterations.
摘要翻译：解码系统包括迭代解码器，其使用奇偶校验约束来迭代地解码由多个码字组成的数据块，以及处理器，其控制迭代解码器以选择性地去除多个解码器迭代的奇偶校验约束的子集，并且包括其他解码器迭代中的一个或多个选择性移除的奇偶校验约束。

10. 发明授权

US08156409B2 Selectively applied hybrid min-sum approximation for constraint node updates of LDPC decoders 有权
标题翻译：对LDPC解码器的约束节点更新进行选择性应用的混合最小和近似
公开(公告)号：US08156409B2
公开(公告)日：2012-04-10
申请号：US12040230
申请日：2008-02-29
申请人： Ara Patapoutian , Rose Y. Shao , Arvind Sridharan
发明人： Ara Patapoutian , Rose Y. Shao , Arvind Sridharan
IPC分类号： H03M13/00
CPC分类号： H03M13/112 , H03M13/3707 , H03M13/6502 , H03M13/6583
摘要： In accordance with one or more embodiments, a decoder may determine whether a lowest reliability value of a plurality of codeword bits that correspond to a particular output reliability value for a particular constraint node of a parity-check matrix is greater than a threshold value (e.g., an offset), and if so, selectively applies a modified min-sum approximation constraint node update with a reliability value modification (e.g., an offset or normalized min-sum approximation).
摘要翻译：根据一个或多个实施例，解码器可以确定对应于奇偶校验矩阵的特定约束节点的特定输出可靠性值的多个码字比特的最低可靠性值是否大于阈值（例如，，偏移），如果是，则选择性地应用具有可靠性值修改（例如，偏移或归一化最小和近似）的经修改的最小和近似约束节点更新。

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