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1. 发明专利

JP2008308765A Damage-free sculptured coating deposition method 审中-公开
标题翻译：无损扫描涂层沉积方法
公开(公告)号：JP2008308765A
公开(公告)日：2008-12-25
申请号：JP2008183140
申请日：2008-07-14
申请人： Applied Materials Inc , アプライドマテリアルズインコーポレイテッドApplied Materials,Incorporated
发明人： CHIANG TONY , YAO GONGDA , DING PEIJUN , CHEN FUSEN , CHIN BARRY , KOHARA GENE , XU ZHENG , ZHANG HONG
IPC分类号： C23C14/34 , H01L21/285 , H01L21/28 , H01L21/768
CPC分类号： H01L21/76843 , C23C14/046 , C23C14/165 , H01L21/2855 , H01L21/76805 , H01L21/76844 , H01L21/76846 , H01L21/76862 , H01L21/76865 , H01L21/76871 , H01L21/76877 , H01L21/76879 , H01L21/76883
摘要： PROBLEM TO BE SOLVED: To provide a method for sputtering and depositing a carrier/barrier layer substantially without contaminating or disturbing the surrounding surface and subjecting the carrier/barrier layer to sculptured coating to achieve a desired shape. SOLUTION: In the method, a sculptured material layer is applied onto a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by collision of ions of a deposited layer. The method comprises a step of applying a first portion of a sculptured layer with a substrate bias sufficiently low for preventing erosion or contamination of the surface onto which the sculptured layer is applied and a step of applying a subsequent portion of the sculptured layer with a substrate bias sufficiently high for sculpturing a shape from the first portion while depositing an additional layer material. The method is particularly applicable to the sculpturing of a barrier layer, a wetting layer, a conductive layer, etc. on a semiconductor feature surface and is especially helpful when the conductive layer is copper. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供基本上不污染或扰乱周围表面的溅射和沉积载体/阻挡层的方法，并使载体/阻挡层经受雕刻的涂层以达到期望的形状。解决方案：在该方法中，使用离子沉积溅射将雕刻材料层施加到半导体特征表面上，其中施加有雕刻层的表面被保护以抵抗通过沉积层的离子的碰撞的侵蚀和污染。该方法包括以下步骤：将具有足够低的衬底偏置的雕刻层的第一部分施加以防止施加雕刻层的表面的侵蚀或污染;以及将基底的随后部分涂覆到衬底偏置足够高以在沉积附加层材料的同时从第一部分雕刻形状。该方法特别适用于半导体特征表面上的阻挡层，润湿层，导电层等的雕刻，并且当导电层为铜时特别有用。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2009010434A Method and apparatus of improving step coverage on substrate at low temperature 审中-公开
标题翻译：在低温条件下改善基层的步骤覆盖的方法和装置
公开(公告)号：JP2009010434A
公开(公告)日：2009-01-15
申请号：JP2008267743
申请日：2008-10-16
申请人： Applied Materials Inc , アプライドマテリアルズインコーポレイテッドApplied Materials,Incorporated
发明人： MOSELY RODERICK CRAIG , ZHANG HONG , CHEN FUSEN , GUO TED
IPC分类号： H01L21/28 , H01L21/285 , C23C14/56 , C23C16/54 , H01L21/3205 , H01L21/677 , H01L21/768
CPC分类号： H01L21/76876 , C23C14/568 , C23C16/54 , H01L21/32051 , H01L21/76843 , H01L21/76877 , H01L21/76879
摘要： PROBLEM TO BE SOLVED: To provide a method of uniforming step coverage on a substrate, and flattening metal layers, and to form continuous, void-free contacts or vias in a sub-half micron application field. SOLUTION: In one embodiment of this invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free. A metallic coating process is preferably carried out in an integrated processing system that includes both PVD and CVD processing chambers so that once the substrate is introduced into a vacuum environment, the metallic coating of the vias and contacts can be carried out without the formation of an oxide layer over the CVD Al layer. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供在基片上均匀化步骤覆盖的方法，以及使金属层变平，并在半微米应用领域中形成连续的无空隙接触或通孔。解决方案：在本发明的一个实施方案中，将难熔层沉积在具有高比例接触或其上形成的通孔的基底上。然后在低温下将CVD金属层沉积到耐火层上，以提供用于PVD金属的保形润湿层。接下来，在低于金属的熔点温度的温度下将PVD金属沉积在先前形成的CVD金属层上。所得到的CVD / PVD金属层基本上无空隙。金属涂覆方法优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将基底引入真空环境中，可以进行通孔和接触的金属涂层而不形成 CVD层上的氧化层。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2010080965A Damage-free sculptured coating deposition method 有权
标题翻译：无损扫描涂层沉积方法
公开(公告)号：JP2010080965A
公开(公告)日：2010-04-08
申请号：JP2009218041
申请日：2009-09-18
申请人： Applied Materials Inc , アプライドマテリアルズインコーポレイテッドApplied Materials,Incorporated
发明人： CHIANG TONY , YAO GONGDA , DING PEIJUN , CHEN FUSEN , CHIN BARRY , KOHARA GENE , XU ZHENG , ZHANG HONG
IPC分类号： H01L21/285 , C23C14/14 , H01L21/28 , H01L21/288 , H01L21/3205 , H01L21/768 , H01L23/52
CPC分类号： H01L21/76843 , C23C14/046 , C23C14/165 , H01L21/2855 , H01L21/76805 , H01L21/76844 , H01L21/76846 , H01L21/76862 , H01L21/76865 , H01L21/76871 , H01L21/76877 , H01L21/76879 , H01L21/76883
摘要： PROBLEM TO BE SOLVED: To provide a method of making a sculptured layer into a desired shape by depositing a sputtered copper seed layer without polluting or disturbing its peripheral surface. SOLUTION: The method of depositing the copper seed layer on a substrate including a plurality of recessed device-features each of which has a bottom portion 516, a sidewall 514, and an upper-side opening 526 has a step (a) for sputter-depositing a first portion of the copper seed layer on the substrate without colliding against the substrate surface portion of the recessed device-feature, in an aspect of causing a sputter from the substrate surface, and a step (b) for sputter-depositing a second portion of the copper seed layer on the substrate, and re-distributing at least a portion of the first portion of the copper seed layer to the bottom portions and the corresponding sidewalls of the plurality of recessed device-features. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过沉积溅射的铜籽晶层而不污染或扰乱其周边表面将雕刻层制成所需形状的方法。解决方案：将铜籽晶层沉积在包括多个具有底部516，侧壁514和上侧开口526的多个凹陷装置特征的基板上的方法具有步骤（a）用于在引起来自衬底表面的溅射的一个方面中溅射沉积衬底上的铜籽晶层的第一部分而不与凹陷器件特征的衬底表面部分相碰撞;以及用于溅射沉积的步骤（b）将铜籽晶层的第二部分沉积在衬底上，并且将铜籽晶层的第一部分的至少一部分重新分配到多个凹陷器件特征的底部部分和相应的侧壁。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JPH1056016A SELECTIVE VIA EMBEDDING USING ANTICORROSION LAYER 失效
公开(公告)号：JPH1056016A
公开(公告)日：1998-02-24
申请号：JP14700997
申请日：1997-04-30
申请人： APPLIED MATERIALS INC
发明人： CHEN LIAN-YUH , GUO TED TIE , HOINKIS MARK , MOSELY RODERICK CRAIG , NAIK MEHUL , ZHANG HONG
IPC分类号： H01L21/285 , H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To simplify the processing step, by forming an anticorrosion layer on the surface of dielectric substance, forming an opening part having the bottom part, wherein a part of the dielectric member or a semiconductor member is exposed, and depositing metal in the opening part by chemical phase deposition of electroplating. SOLUTION: A layer structure 30 includes a dielectric layer 32 and an anticorrosion layer 34, which are sequentially formed on a dielectric member or dielectric layer 36. A window part at the resist layer of the structure 30 exposes the anticorrosion layer 34. Therefore, an opening part is etched ands passes the anticorrosion layer 34 and the dielectric layer 32. Then, the anticorrosion layer 34 and the dielectric layer 32 is etched, and the opening part having the bottom part, wherein deposition intensifying material us exposed, is formed. This opening part is etched through the dielectric layer 32. A wall part 40 and a bottom part 42, wherein at least a part of the dielectric member 36 is exposed, are formed. When the chemical phase deposition is performed on the substrate, on which the pattern in formed, the selective deposition is provided in the opening part.

5. 发明专利

JPH09172085A METHOD AND DEVICE FOR IMPROVING STEP COVERAGE OF SUBSTRATE AT LOW TEMPERATURE 失效
公开(公告)号：JPH09172085A
公开(公告)日：1997-06-30
申请号：JP29598396
申请日：1996-11-08
申请人： APPLIED MATERIALS INC
发明人： MOSELY RODERICK CRAIG , ZHANG HONG , CHEN FUSEN , GUO TED
IPC分类号： H01L21/285 , C23C14/56 , C23C16/54 , H01L21/28 , H01L21/3205 , H01L21/677 , H01L21/768 , H01L21/68
摘要： PROBLEM TO BE SOLVED: To make it possible to flatten the surface of an aperture formed in a substrate by a method wherein a titanium layer having a specified thickness is sputtered over the surface of the aperture, an aluminum film having a specified thickness is chemically deposited on the surface of the titanium layer and the aluminum film is subjected to physical growth at a specified low temperature and is fluidized in a via hole. SOLUTION: An Al layer formed by a PVD method is deposited on an Al layer formed by a CVD method and a PVD layer 23 is formed on the Al layer formed by the CVD method. A mixed Al layer formed by the CVD and PVD methods is one generated by a method wherein when the Al layer formed by the CVD method is deposited on the Al layer formed by the CVD method, the Al layers are mixed with each other. The Al layer formed by the PVD method contains a constant dopant and when the Al layer is deposited on the Al layer formed by the CVD method, both of the Al layers are mixed with each other, the dopant is dispersed in the whole mixed layer and the top surface 26 of the mixed layer 24 can be flattened. As a titanium layer gives a wettability to the Al layers, there is no need for the temperature of an insulating layer during the deposition of the Al layer formed by the PVD method, that is, a wafer, to exceed the melting point of 660 deg.C of aluminum and it is preferable that the temperature is a temperature (440 deg.C) lower than the 660 deg.C.

6. 发明申请

WO2004100231A2 OBLIQUE ION MILLING OF VIA METALLIZATION 审中-公开
标题翻译：通过金属化的极限离子铣削
公开(公告)号：WO2004100231A2
公开(公告)日：2004-11-18
申请号：PCT/US2004014406
申请日：2004-05-04
申请人： APPLIED MATERIALS INC
发明人： GOPALRAJA PRABURAM , TANG XIANMIN , FU JIANMING , PERRIN MARK A , WANG JEAN YUE PHILLIP , SUNDARRAJAN ARVIND , ZHANG HONG , YU JICK , KELKAR UMESH , XU ZHENG , CHEN FUSEN
IPC分类号： C23C14/04 , C23C14/34 , C23C14/46 , C23C14/58 , H01J37/305 , H01J37/34 , H01L21/285 , H01L21/768 , H01L21/00
CPC分类号： H01J37/34 , C23C14/046 , C23C14/3442 , C23C14/5833 , H01J37/3053 , H01L21/2855 , H01L21/76843 , H01L21/76862 , H01L21/76865
摘要： In conjunction with sputtering a metal, especially copper, into high aspect-ratio holes in a wafer, an oblique ion milling method in which argon ions or other particles having energies in the range of 200 to 1500e V are directed to the wafer at between 10 and 35° to the wafer surface to sputter etch material sputter deposited preferentially on the upper corners of the holes. The milling may be performed in the sputter deposition chamber either simultaneously with the deposition or after it or performed afterwards in a separate milling reactor. A plurality of ion sources arranged around the chamber improve angular uniformity or arranged axially improve radial uniformity or vary the angle of incidence. An annular ion source about the chamber axis allows a plasma current loop. Anode layer ion sources and sources composed of copper are advantageous.
摘要翻译：结合将金属，特别是铜溅射到晶片中的高纵横比孔中，其中具有在200至1500eV范围内的能量的氩离子或其它颗粒的倾斜离子研磨方法在10 并且与晶片表面成35°的溅射蚀刻材料溅射沉积优先在孔的上角上。研磨可以在溅射沉积室中同时进行沉积，或者在沉积之后或之后在单独的研磨反应器中进行。围绕腔室布置的多个离子源提高了角度均匀性或者轴向地改变径向均匀性或改变入射角。围绕腔室轴线的环形离子源允许等离子体电流回路。阳极层离子源和由铜组成的源是有利的。

7. 发明申请

WO2006121604A3 CONDUCTIVE BARRIER LAYER, ESPECIALLY AN ALLOY OF RUTHENIUM AND TANTALUM AND SPUTTER DEPOSITION THEREOF 审中-公开
标题翻译：导电阻隔层，特别是钌和钽的合金和溅射沉积物
公开(公告)号：WO2006121604A3
公开(公告)日：2007-09-13
申请号：PCT/US2006015523
申请日：2006-04-25
申请人： APPLIED MATERIALS INC , WANG JENN YUE , WANG WEL D , WANG RONGJIUM , TANAKA YOICHIRO , CHUNG HUA , ZHANG HONG , YU JICK , GOPALRAJA PRABURAM , FU JIANMING
发明人： WANG JENN YUE , WANG WEL D , WANG RONGJIUM , TANAKA YOICHIRO , CHUNG HUA , ZHANG HONG , YU JICK , GOPALRAJA PRABURAM , FU JIANMING
IPC分类号： C23C14/34 , H01L21/44 , H01L27/095
CPC分类号： B32B15/018 , C23C14/3414 , H01L21/2855 , H01L21/76844 , H01L23/53238 , H01L2924/0002 , Y10T428/24917 , H01L2924/00
摘要： A fabrication method, a product structure, a fabrication method, and a sputtering target for the deposition of a conductive barrier or other liner layer in an interconnect structure. The barrier layer (82) comprises a conductive metal of a refractory noble metal alloy, such as a ruthenium/tantalum alloy, which may be amorphous though it is not require to be so. The barrier layer may be sputtered from a target (90) of similar composition. The barrier and target composition may be chosen from a combination of the refractory metals and the platinum-group metals as well as RuTa. A copper noble seed layer (112) may be formed of an alloy of copper and ruthenium in contact to a barrier layer (70) over the dielectric (66).
摘要翻译：用于在互连结构中沉积导电屏障或其它衬垫层的制造方法，产品结构，制造方法和溅射靶。阻挡层（82）包括诸如钌/钽合金的难熔贵金属合金的导电金属，其可以是无定形的，尽管不需要这样。阻挡层可以从类似组成的靶（90）溅射。阻挡层和靶组成可以选自难熔金属和铂族金属以及RuTa的组合。铜高贵种子层（112）可以由铜和钌的合金形成，与电介质（66）上的阻挡层（70）接触。

8. 发明申请

WO2010059857A3 BOTTOM UP PLATING BY ORGANIC SURFACE PASSIVATION AND DIFFERENTIAL PLATING RETARDATION 审中-公开
标题翻译：有机表面钝化和不均匀镀层延展的底层
公开(公告)号：WO2010059857A3
公开(公告)日：2010-08-19
申请号：PCT/US2009065193
申请日：2009-11-19
申请人： APPLIED MATERIALS INC , WANG JENN-YUE , CHUNG HUA , TAO RONG , ZHANG HONG
发明人： WANG JENN-YUE , CHUNG HUA , TAO RONG , ZHANG HONG
IPC分类号： H01L21/288
CPC分类号： H01L21/76877 , C25D5/022 , C25D5/10 , H01L21/2885 , H01L21/321 , H01L2221/1063
摘要： Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. One embodiment provides a method provides a method for processing a substrate comprising forming a seed layer over a substrate having trench or via structures formed therein, coating a portion of the seed layer with an organic passivation film, and immersing the trench or via structures in a plating solution to deposit a conductive material over the seed layer not covered by the organic passivation film.
摘要翻译：本发明的实施例一般涉及用于处理半导体衬底的装置和方法。一个实施例提供了一种提供用于处理衬底的方法的方法，包括在其上形成有沟槽或通孔结构的衬底上形成晶种层，用有机钝化膜涂覆种子层的一部分，以及将沟槽或通孔结构浸入电镀溶液以在未被有机钝化膜覆盖的种子层上沉积导电材料。

9. 发明公开

EP0776037A3 Low temperature integrated metallization process and apparatus 失效
标题翻译： Integriertes Niedrig-Temperatur-Metallisierungsverfahren und Vorrichtung
公开(公告)号：EP0776037A3
公开(公告)日：1998-05-13
申请号：EP96116941
申请日：1996-10-22
申请人： APPLIED MATERIALS INC
发明人： MOSELY RODERICK CRAIG , ZHANG HONG , CHEN FUSEN , GUO TED
IPC分类号： H01L21/285 , C23C14/56 , C23C16/54 , H01L21/28 , H01L21/3205 , H01L21/677 , H01L21/768
CPC分类号： H01L21/76876 , C23C14/568 , C23C16/54 , H01L21/32051 , H01L21/76843 , H01L21/76877 , H01L21/76879
摘要： The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer (16) is deposited onto a substrate having high aspect ratio contacts or vias (14) formed thereon. A CVD metal layer (22) is then deposited onto the refractory layer (16) at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal (23) is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer (24) is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Al layer.
摘要翻译：本发明一般涉及在衬底上提供均匀的台阶覆盖和金属层的平坦化以在半微米应用中形成连续的无空隙触点或通孔的改进方法。在本发明的一个方面，将耐火层（16）沉积到具有高纵横比的触点或其上形成的通孔（14）的基板上。然后将CVD金属层（22）在低温下沉积到耐火层（16）上，以提供用于PVD金属的保形润湿层。接下来，在低于金属的熔点温度的温度下，将PVD金属（23）沉积在预先形成的CVD金属层上。所得到的CVD / PVD金属层（24）基本上无空隙。金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，就会发生通孔和触点的金属化，而不会在其上形成氧化物层 CVD Al层。

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