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1. 发明申请

US20170168520A1 Timebase Synchronization 有权
公开(公告)号：US20170168520A1
公开(公告)日：2017-06-15
申请号：US14965073
申请日：2015-12-10
申请人： Apple Inc.
发明人： Shu-Yi Yu , Erik P. Machnicki , Gilbert H. Herbeck , Kiran B. Kattel , Manu Gulati
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F1/14
摘要： In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.

2. 发明申请

US20180107240A1 Timebase Synchronization 审中-公开
公开(公告)号：US20180107240A1
公开(公告)日：2018-04-19
申请号：US15831732
申请日：2017-12-05
申请人： Apple Inc.
发明人： Shu-Yi Yu , Erik P. Machnicki , Gilbert H. Herbeck , Kiran B. Kattel , Manu Gulati
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F1/14
摘要： In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.

3. 发明申请

US20160291625A1 Under Voltage Detection and Performance Throttling 有权
标题翻译：欠压检测和性能调节
公开(公告)号：US20160291625A1
公开(公告)日：2016-10-06
申请号：US14673326
申请日：2015-03-30
申请人： Apple Inc.
发明人： Brijesh Tripathi , Eric G. Smith , Erik P. Machnicki , Jung Wook Cho , Khaled M. Alashmouny , Kiran B. Kattel , Vijay M. Bettada , Bo Yang , Wenlong Wei
IPC分类号： G05F3/02
CPC分类号： G05F3/02 , G06F1/324 , G06F1/3296
摘要： An under voltage detection circuit and method of operating an IC including the same is disclosed. In one embodiment, an IC includes an under voltage protection circuit having first and second comparators configured to compare a supply voltage to first and second voltage thresholds, respectively, with the second voltage threshold being greater than the first. A logic circuit is coupled to receive signals from the first and second comparators. During operation in a high performance state by a corresponding functional circuit, the logic circuit is configured to cause assertion of a throttling signal responsive to an indication that the supply voltage has fallen below the first threshold. A clock signal provided to the functional circuit may be throttled responsive to the indication. If the supply voltage subsequently rises to a level above the second threshold, the throttling signal may be de-asserted.
摘要翻译：公开了一种欠压检测电路及其运算方法。在一个实施例中，IC包括欠压保护电路，其具有第一和第二比较器，其被配置为分别将电源电压与第一和第二电压阈值进行比较，其中第二电压阈值大于第一电压阈值。逻辑电路被耦合以从第一和第二比较器接收信号。在通过相应的功能电路在高性能状态下操作期间，逻辑电路被配置为响应于电源电压已经低于第一阈值的指示而导致节流信号的断言。提供给功能电路的时钟信号可以响应于指示而被节流。如果电源电压随后上升到高于第二阈值的水平，则节流信号可以被取消断言。

4. 发明授权

US10048720B2 Timebase synchronization 有权
公开(公告)号：US10048720B2
公开(公告)日：2018-08-14
申请号：US15831732
申请日：2017-12-05
申请人： Apple Inc.
发明人： Shu-Yi Yu , Erik P. Machnicki , Gilbert H. Herbeck , Kiran B. Kattel , Manu Gulati
IPC分类号： G06F1/12
摘要： In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.

5. 发明授权

US09864399B2 Timebase synchronization 有权
公开(公告)号：US09864399B2
公开(公告)日：2018-01-09
申请号：US14965073
申请日：2015-12-10
申请人： Apple Inc.
发明人： Shu-Yi Yu , Erik P. Machnicki , Gilbert H. Herbeck , Kiran B. Kattel , Manu Gulati
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F1/14
摘要： In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.

6. 发明授权

US09658634B2 Under voltage detection and performance throttling 有权
公开(公告)号：US09658634B2
公开(公告)日：2017-05-23
申请号：US14673326
申请日：2015-03-30
申请人： Apple Inc.
发明人： Brijesh Tripathi , Eric G. Smith , Erik P. Machnicki , Jung Wook Cho , Khaled M. Alashmouny , Kiran B. Kattel , Vijay M. Bettada , Bo Yang , Wenlong Wei
IPC分类号： G06F1/00 , G05F3/02 , G06F1/32
CPC分类号： G05F3/02 , G06F1/324 , G06F1/3296
摘要： An under voltage detection circuit and method of operating an IC including the same is disclosed. In one embodiment, an IC includes an under voltage protection circuit having first and second comparators configured to compare a supply voltage to first and second voltage thresholds, respectively, with the second voltage threshold being greater than the first. A logic circuit is coupled to receive signals from the first and second comparators. During operation in a high performance state by a corresponding functional circuit, the logic circuit is configured to cause assertion of a throttling signal responsive to an indication that the supply voltage has fallen below the first threshold. A clock signal provided to the functional circuit may be throttled responsive to the indication. If the supply voltage subsequently rises to a level above the second threshold, the throttling signal may be de-asserted.

7. 发明授权

US09286961B1 Memory controller half-clock delay adjustment 有权
标题翻译：内存控制器半时钟延迟调整
公开(公告)号：US09286961B1
公开(公告)日：2016-03-15
申请号：US14672412
申请日：2015-03-30
申请人： Apple Inc.
发明人： Robert E. Jeter , Rakesh L. Notani , Kiran B. Kattel
IPC分类号： G11C7/22 , G11C8/18 , H03L7/08
CPC分类号： H03L7/08 , G11C7/1093 , G11C7/22
摘要： A method and apparatus for reducing a number of delay elements used in providing a delayed data strobe signal is disclosed. The method includes determining a number of delay elements of a master delay locked loop (DLL) needed to provide a calibrated delay of a clock signal (i.e. the data strobe). The method also include determining an integer number of half clock periods within the calibrated delay, and determining a second number of delay elements within the calibrated delay. If the integer number of half clock periods within the calibrated delay is zero, a slave DLL may be programmed with the first number of delay elements. However, if the number of half clock periods is non-zero, then a third number of delay elements is calculated by subtracting the second number of delay elements from the first number. Thereafter, the slave DLL is programmed with the third number of delay elements.
摘要翻译：公开了一种用于减少用于提供延迟的数据选通信号的延迟元件的数量的方法和装置。该方法包括确定提供时钟信号（即，数据选通）的校准延迟所需的主延迟锁定环（DLL）的延迟元件的数量。该方法还包括确定校准延迟内的半个时钟周期的整数，以及确定校准延迟内的第二数量的延迟元件。如果校准延迟内的半个时钟周期的整数为零，则可以用第一数量的延迟元件对从属DLL进行编程。然而，如果半个时钟周期的数量是非零，则通过从第一个数字减去第二个延迟元素数来计算第三个延迟元件数。此后，从动DLL用第三数量的延迟元件编程。

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