专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06594699B1 System for capability based multimedia streaming over a network 失效
标题翻译：通过网络实现基于能力的多媒体流的系统
公开(公告)号：US06594699B1
公开(公告)日：2003-07-15
申请号：US08948668
申请日：1997-10-10
申请人： Anupam Sahai , Ram K. Gupta , Jitendra Kothari
发明人： Anupam Sahai , Ram K. Gupta , Jitendra Kothari
IPC分类号： G06F1300
CPC分类号： H04L65/4084 , H04L29/06027 , H04L65/602 , H04L65/80 , H04L67/303 , H04L69/24
摘要： The present invention is a system in which packet-switched (or general purpose network) multimedia data streaming is controlled based on the capabilities of a client and the preferences of a user. A server processor, coupled to the client processor over a packet-switched network, such as the Internet, receives client processor capabilities in association with a request for service for a multimedia type data transfer. The capabilities can be obtained by an application running on the client assessing the capabilities or through prompting of the user. The client capabilities include, for example, processor speed and multimedia encoders of the client. The server can also obtain the preferences of the user of the client processor and respond based on the preferences. Preferences include, for example, the quality of service of the transfer. The capabilities and preferences can be obtained via a query from the server to the client or can be automatically sent with each request. The data format is chosen, the data is adapted and transferred over the network by the server responsive to the capabilities and preferences and played to the user by the client.
摘要翻译：本发明是基于客户端的能力和用户偏好来控制分组交换（或通用网络）多媒体数据流的系统。通过分组交换网络（诸如因特网）耦合到客户机处理器的服务器处理器与多媒体类型数据传输的服务请求相关联地接收客户端处理器能力。可以通过在客户端上运行的应用程序来评估功能或通过提示用户来获得这些功能。客户端功能包括例如客户机的处理器速度和多媒体编码器。服务器还可以获得客户端处理器的用户的偏好，并根据偏好进行响应。偏好包括例如转移服务的质量。功能和偏好可以通过从服务器到客户端的查询获得，或者可以自动发送每个请求。选择数据格式，响应于能力和偏好，由服务器通过网络对数据进行调整和传输，并由客户端向用户播放。

3. 发明授权

US6098162A Vector shift functional unit for successively shifting operands stored in a vector register by corresponding shift counts stored in another vector register 有权
标题翻译：向量移位功能单元，用于通过存储在另一向量寄存器中的相应移位计数连续移位存储在向量寄存器中的操作数
公开(公告)号：US6098162A
公开(公告)日：2000-08-01
申请号：US138613
申请日：1998-08-24
申请人： Alan J. Schiffleger , Ram K. Gupta , Christopher C. Hsiung
发明人： Alan J. Schiffleger , Ram K. Gupta , Christopher C. Hsiung
IPC分类号： G06F9/315 , G06F15/78 , G06F9/15
CPC分类号： G06F9/30032 , G06F15/8076 , G06F9/30036
摘要： Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shift count for each operand. Operands and shift counts are successively transferred to a vector shift functional unit, which shifts the operand by an amount equal to the value of the shift count. The shifted operands are stored in a third vector register. The vector shift functional unit also achieves word shifting of a predetermined number of vector register elements to different word locations of another vector register.
摘要翻译：在矢量超级计算机处理器中实现向量寄存器的向量寄存器的向量移位元件。第一个向量寄存器包含一组操作数，第二个向量寄存器包含一组移位计数，每个操作数一个移位计数。操作数和移位计数依次传送到向量移位功能单元，该单元将操作数移位一个等于移位计数值的量。移位的操作数存储在第三个向量寄存器中。矢量移位功能单元还实现了预定数量的矢量寄存器元件到另一向量寄存器的不同字位置的字移位。

4. 发明授权

US5606696A Exception handling method and apparatus for a microkernel data processing system 失效
标题翻译：用于微内核数据处理系统的异常处理方法和装置
公开(公告)号：US5606696A
公开(公告)日：1997-02-25
申请号：US533455
申请日：1995-09-25
申请人： Dennis F. Ackerman , Himanshu H. Desai , Ram K. Gupta , Ravi R. Srinivasan
发明人： Dennis F. Ackerman , Himanshu H. Desai , Ram K. Gupta , Ravi R. Srinivasan
IPC分类号： G06F9/46 , G06F9/48
CPC分类号： G06F9/4812 , G06F9/4843
摘要： Floating point hardware register set is not given to any user level thread unless it is required to perform floating point operations. Thus, for any non-floating thread, its context does not include the floating point hardware state. This effectively reduces the amount of information to be handled when threads are swapped in the processor. During the course of a thread's execution, at the first instance of an attempt by the thread to execute a floating point instruction, the "float-unavailable" exception occurs. This, in turn, invokes the microkernel's floating point exception handler. The function of this exception handler is to make floating point available to the thread that requires it. The exception handler dynamically allocates space for saving the thread's floating point registers, initializes the registers, and turns on the "float-available" bit in its machine state register. Once a thread obtains floating point context, it continues to have it for the remainder of its life.
摘要翻译：除非需要执行浮点运算，否则浮点硬件寄存器集不会被给予任何用户级线程。因此，对于任何非浮动线程，其上下文不包括浮点硬件状态。这有效地减少了在处理器中交换线程时要处理的信息量。在执行线程的过程中，在线程尝试执行浮点指令的第一个实例中，发生“float-unavailable”异常。这反过来调用微内核的浮点异常处理程序。此异常处理程序的功能是使浮点可用于需要的线程。异常处理程序动态分配空间以保存线程的浮点寄存器，初始化寄存器，并打开其机器状态寄存器中的“浮动可用”位。一旦线程获得浮点上下文，它将在剩余的时间内继续存在。

5. 发明授权

US5247637A Method and apparatus for sharing memory in a multiprocessor system 失效
标题翻译：用于在多处理器系统中共享存储器的方法和装置
公开(公告)号：US5247637A
公开(公告)日：1993-09-21
申请号：US531861
申请日：1990-06-01
申请人： George W. Leedom , Alan J. Schiffleger , Ram K. Gupta
发明人： George W. Leedom , Alan J. Schiffleger , Ram K. Gupta
IPC分类号： G06F15/173
CPC分类号： G06F15/173
摘要： The present invention provides a memory interface system wherein there is provided a memory having multiple ports and divided into sections, with each section divided into subsections, with memory banks within each subsection, and the banks divided into at least two bank groups. The invention further provided a memory interface for controlling the referencing of said memory banks according to which bank group they are in.
摘要翻译：本发明提供了一种存储器接口系统，其中提供了具有多个端口并被划分为多个部分的存储器，每个部分被划分成子部分，每个子部分内的存储体，并且划分成至少两个组组的存储体。本发明还提供了一种存储器接口，用于根据它们所在的银行组来控制所述存储器组的参考。

6. 发明授权

US4159519A Template family interfacing structure for providing a sequence of microinstructions to a pipelined microprogrammable data processing system 失效
标题翻译：模板族接口结构，用于向流水线可编程数据处理系统提供一系列微指令
公开(公告)号：US4159519A
公开(公告)日：1979-06-26
申请号：US853518
申请日：1977-11-21
申请人： Ram K. Gupta
发明人： Ram K. Gupta
IPC分类号： G06F9/28 , G06F9/22 , G06F9/26 , G06F9/38 , G06F9/16 , G06F13/00
CPC分类号： G06F9/262
摘要： In a microprogrammed pipelined data processing system, a template family interfacing structure sequences a plurality of templates to the pipelined system for control thereof, each template therein comprising a set of microinstructions for controlling each stage in the pipelined system. The templates are stored in a template micromemory system addressed by an address register and read to a control register. Parameters, grouped into template "Families", of the next template to be used and family parameters of the current template in use are utilized in conjunction to control the initiation of the next template to avoid conflict in any stage in the pipelined system.
摘要翻译：在微程序流水线数据处理系统中，模板族接口结构将多个模板序列到流水线系统以进行控制，其中的每个模板包括用于控制流水线系统中的每个级的一组微指令。模板存储在由地址寄存器寻址的模板微存储系统中，并读取到控制寄存器。将要使用的下一个模板的分组模板“家族”和正在使用的当前模板的系列参数的参数结合使用，以控制下一个模板的启动，以避免流水线系统中任何阶段的冲突。

7. 发明授权

US5848286A Vector word shift by vo shift count in vector supercomputer processor 失效
标题翻译：向量超级计算机处理器中的矢量字移位
公开(公告)号：US5848286A
公开(公告)日：1998-12-08
申请号：US521566
申请日：1995-08-30
申请人： Alan J. Schiffleger , Ram K. Gupta , Christopher C. Hsiung
发明人： Alan J. Schiffleger , Ram K. Gupta , Christopher C. Hsiung
IPC分类号： G06F9/315 , G06F15/78 , G06F15/16
CPC分类号： G06F9/30032 , G06F15/8076 , G06F9/30036
摘要： Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shift count for each operand. Operands and shift counts are successively transferred to a vector shift functional unit, which shifts the operand by an amount equal to the value of the shift count. The shifted operands are stored in a third vector register. The vector shift functional unit also achieves word shifting of a predetermined number of vector register elements to different word locations of another vector register.
摘要翻译：在矢量超级计算机处理器中实现向量寄存器的向量寄存器的向量移位元件。第一个向量寄存器包含一组操作数，第二个向量寄存器包含一组移位计数，每个操作数一个移位计数。操作数和移位计数依次传送到向量移位功能单元，该单元将操作数移位一个等于移位计数值的量。移位的操作数存储在第三个向量寄存器中。矢量移位功能单元还实现了预定数量的矢量寄存器元件到另一向量寄存器的不同字位置的字移位。

8. 发明授权

US5481746A Vector shift functional unit for successively shifting operands stored in a vector register by corresponding shift counts stored in another vector register 失效
公开(公告)号：US5481746A
公开(公告)日：1996-01-02
申请号：US218997
申请日：1994-03-29
申请人： Alan J. Schiffleger , Ram K. Gupta , Christopher C. Hsiung
发明人： Alan J. Schiffleger , Ram K. Gupta , Christopher C. Hsiung
IPC分类号： G06F9/315 , G06F15/78 , G06F9/30 , G06F9/302
CPC分类号： G06F9/30032 , G06F15/8076 , G06F15/8084 , G06F9/30036
摘要： Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shift count for each operand. Operands and shift counts are successively transferred to a vector shift functional unit, which shifts the operand by an amount equal to the value of the shift count. The shifted operands are stored in a third vector register. The vector shift functional unit also achieves word shifting of a predetermined number of vector register elements to different word locations of another vector register.

9. 发明授权

US5481719A Exception handling method and apparatus for a microkernel data processing system 失效
标题翻译：用于微内核数据处理系统的异常处理方法和装置
公开(公告)号：US5481719A
公开(公告)日：1996-01-02
申请号：US303796
申请日：1994-09-09
申请人： Dennis F. Ackerman , Himanshu H. Desai , Ram K. Gupta , Ravi R. Srinivasan
发明人： Dennis F. Ackerman , Himanshu H. Desai , Ram K. Gupta , Ravi R. Srinivasan
IPC分类号： G06F9/46 , G06F9/48 , G06F9/44
CPC分类号： G06F9/4812 , G06F9/4843
摘要： Floating point hardware register set is not given to any user level thread unless it is required to perform floating point operations. Thus, for any non-floating thread, its context does not include the floating point hardware state. This effectively reduces the amount of information to be handled when threads are swapped in the processor. During the course of a thread's execution, at the first instance of an attempt by the thread to execute a floating point instruction, the "float-unavailable" exception occurs. This, in turn, invokes the microkernel's floating point exception handler. The function of this exception handler is to make floating point available to the thread that requires it. The exception handler dynamically allocates space for saving the thread's floating point registers, initializes the registers, and turns on the "float-available" bit in its machine state register. Once a thread obtains floating point context, it continues to have it for the remainder of its life.
摘要翻译：除非需要执行浮点运算，否则浮点硬件寄存器集不会被给予任何用户级线程。因此，对于任何非浮动线程，其上下文不包括浮点硬件状态。这有效地减少了在处理器中交换线程时要处理的信息量。在执行线程的过程中，在线程尝试执行浮点指令的第一个实例中，发生“float-unavailable”异常。这反过来调用微内核的浮点异常处理程序。此异常处理程序的功能是使浮点可用于需要的线程。异常处理程序动态分配空间以保存线程的浮点寄存器，初始化寄存器，并打开其机器状态寄存器中的“浮动可用”位。一旦线程获得浮点上下文，它将在剩余的时间内继续存在。

10. 发明授权

US4228497A Template micromemory structure for a pipelined microprogrammable data processing system 失效
标题翻译：用于流水线微程序数据处理系统的模板微存储结构
公开(公告)号：US4228497A
公开(公告)日：1980-10-14
申请号：US838070
申请日：1977-11-17
申请人： Ram K. Gupta , Chandrakant R. Vora
发明人： Ram K. Gupta , Chandrakant R. Vora
IPC分类号： G06F7/00 , G06F9/22 , G06F9/28 , G06F9/38 , G06F13/00
CPC分类号： G06F9/28 , G06F9/3867
摘要： In a microprogrammed data processing pipeline system comprising a plurality of stages, microinstructions for controlling the stages are stored as templates in an addressable template micromemory store and are provided automatically and sequentially to the stage of the pipeline system. Each template is associated with an individual set of data and includes microinstructions for each stage, whether real or virtual, through which the associated set of data passes. The template micromemory store is segmented into a plurality of individually addressable micromemory units with each unit therein storing microinstructions for an individually associated stage in the data processing pipeline system.
摘要翻译：在包括多个级的微程序数据处理流水线系统中，用于控制级的微指令作为模板存储在可寻址模板微存储器中，并且被自动且顺序地提供给流水线系统的级。每个模板与单独的数据集相关联，并且包括用于每个阶段的微指令，无论是实数还是虚拟的，相关联的数据集通过该微指令。模板微存储器被分割成多个单独可寻址的微存储单元，其中每个单元存储数据处理流水线系统中单独相关级的微指令。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式