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1. 发明授权

US5317657A Extrusion of polymer waveguides onto surfaces 失效
标题翻译：将聚合物波导挤出到表面上
公开(公告)号：US5317657A
公开(公告)日：1994-05-31
申请号：US922267
申请日：1992-07-30
申请人： Antonio R. Gallo , James J. McDonough , Gordon J. Robbins , Robert R. Shaw
发明人： Antonio R. Gallo , James J. McDonough , Gordon J. Robbins , Robert R. Shaw
IPC分类号： B29C41/36 , B29C47/00 , B29C67/00 , B29D11/00 , G02B6/122 , G02B6/13 , G02B6/132 , G02B6/138
CPC分类号： B29C47/0004 , B29C41/36 , B29D11/00663 , G02B6/1221 , G02B6/132 , G02B6/138 , B29C47/0009 , B29C67/00
摘要： A waveguide structure is directly extruded onto a surface from a nozzle placed a predetermined distance above the surface and which is moved relative to the surface, preferably by means of a translation table. The predetermined distance is preferably maintained constant and the speed of relative motion regulated to achieve a uniform degree of molecular orientation within the extruded material, thus maintaining a sufficiently uniform refractive index along the axis of the waveguide. Partitions within the nozzle allow the formation of a layered waveguide or the simultaneous formation of concentric cladding or protective layers. The waveguides are advantageously formed as a curtain which is later patterned, by direct writing on the surface or between chips mounted on an electronic module.
摘要翻译：波导结构直接从位于表面上方预定距离的喷嘴的表面挤出，并且相对于表面移动，优选地通过平移台。预定距离优选地保持恒定并且相对运动的速度被调节以在挤出的材料内实现均匀的分子取向程度，从而沿着波导的轴保持足够均匀的折射率。喷嘴内的分区允许形成分层波导或同时形成同心包层或保护层。波导有利地形成为帘幕，其通过直接写在表面上或安装在电子模块上的芯片之间而被图案化。

2. 发明授权

US5208879A Optical signal distribution system 失效
标题翻译：光信号分配系统
公开(公告)号：US5208879A
公开(公告)日：1993-05-04
申请号：US779428
申请日：1991-10-18
申请人： Antonio R. Gallo , Gordon J. Robbins , Robert R. Shaw
发明人： Antonio R. Gallo , Gordon J. Robbins , Robert R. Shaw
IPC分类号： G02B6/00 , G02B6/12 , G02B6/122 , G02B6/42 , H01L27/15 , H04B10/02 , H04B10/12
CPC分类号： G02B6/12004
摘要： Disclosed is an optical signal distribution system. The system comprises an electronic substrate, at least one optical component and at least one optical waveguide on but distinct from the electronic substrate for carrying an optical signal to or from the optical component.
摘要翻译：公开了一种光信号分配系统。该系统包括电子基板，至少一个光学部件和至少一个光电波导，所述至少一个光波导与电子基板但不同，用于将光信号传送到光学部件或从光学部件传送光信号。

3. 发明授权

US5757079A Method for repairing defective electrical connections on multi-layer thin film (MLTF) electronic packages and the resulting MLTF structure 失效
标题翻译：修复多层薄膜（MLTF）电子封装上有缺陷的电气连接以及由此产生的MLTF结构的方法
公开(公告)号：US5757079A
公开(公告)日：1998-05-26
申请号：US577677
申请日：1995-12-21
申请人： Michael McAllister , James McDonald , Eric Daniel Perfecto , Chandrika Prasad , Keshav Prasad , Gordon J. Robbins , Madhavan Swaminathan , George Eugene White
发明人： Michael McAllister , James McDonald , Eric Daniel Perfecto , Chandrika Prasad , Keshav Prasad , Gordon J. Robbins , Madhavan Swaminathan , George Eugene White
IPC分类号： H01L21/48 , H01L23/538 , H05K3/00 , H05K3/22 , H05K3/46 , H01L23/48 , H01L23/52 , H01L23/58 , H01L29/40
CPC分类号： H01L23/5382 , H01L21/485 , H05K3/225 , H01L2924/0002 , H01L2924/09701 , H05K2203/162 , H05K3/0082 , H05K3/4644
摘要： A multi-layer thin film structure having defined repair lines thereon and a method for repairing interconnections in the multi-layer thin film structure (MLTF) and/or making engineering charges (EC) are provided. The method comprises determining any interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, using lithography, e.g., direct write expose technology, to define the top surface connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization and repair lines using additive or substractive metallization techniques.
摘要翻译：提供了一种具有定义的修补线的多层薄膜结构和用于修复多层薄膜结构（MLTF）中的互连和/或制造工程电荷（EC）的方法。该方法包括使用光刻技术（例如直接写入曝光技术）来确定在与结构的顶部金属层相邻的薄膜层处的MLTF中的任何互连缺陷，以限定修复互连所需的顶面连接和/或使EC ，并使用添加剂或阴极金属化技术形成顶表面金属化和修补线。

4. 发明授权

US5747095A Method for repairing defective electrical connections on multi-layer thin film (MLTF) electronic packages 失效
标题翻译：修复多层薄膜（MLTF）电子封装上有缺陷的电气连接的方法
公开(公告)号：US5747095A
公开(公告)日：1998-05-05
申请号：US800945
申请日：1997-02-14
申请人： Michael McAllister , Eric Daniel Perfecto , James McDonald , Keshav Prasad , Gordon J. Robbins , Chandrika Prasad , Madhavan Swaminathan , George Eugene White
发明人： Michael McAllister , Eric Daniel Perfecto , James McDonald , Keshav Prasad , Gordon J. Robbins , Chandrika Prasad , Madhavan Swaminathan , George Eugene White
IPC分类号： H01L21/48 , H01L23/538 , H05K3/00 , H05K3/22 , H05K3/46 , B05D5/12
CPC分类号： H01L23/5382 , H01L21/485 , H05K3/225 , H01L2924/0002 , H01L2924/09701 , H05K2203/162 , H05K3/0082 , H05K3/4644
摘要： A multi-layer thin film structure having defined repair lines thereon and a method for repairing interconnections in the multi-layer thin film structure (MLTF) and/or making engineering charges (EC) are provided. The method comprises determining any interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, using lithography, e.g., direct write expose technology, to define the top surface connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization and repair lines using additive or substractive metallization techniques.
摘要翻译：提供了一种具有定义的修补线的多层薄膜结构和用于修复多层薄膜结构（MLTF）中的互连和/或制造工程电荷（EC）的方法。该方法包括使用光刻技术（例如直接写入曝光技术）来确定在与结构的顶部金属层相邻的薄膜层处的MLTF中的任何互连缺陷，以限定修复互连所需的顶面连接和/或使EC ，并使用添加剂或阴极金属化技术形成顶表面金属化和修补线。

5. 发明授权

US5378927A Thin-film wiring layout for a non-planar thin-film structure 失效
标题翻译：非平面薄膜结构的薄膜布线布局
公开(公告)号：US5378927A
公开(公告)日：1995-01-03
申请号：US65385
申请日：1993-05-24
申请人： Michael F. McAllister , James A. McDonald , Keshav Prasad , Gordon J. Robbins , Madhavan Swaminathan
发明人： Michael F. McAllister , James A. McDonald , Keshav Prasad , Gordon J. Robbins , Madhavan Swaminathan
IPC分类号： H01L23/12 , H01L21/768 , H01L23/522 , H01L23/538 , H01L23/50 , H01L23/52
CPC分类号： H01L23/5384 , H01L23/5386 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011
摘要： A thin-film arrangement for a non-planar structure is described. The structure includes a substrate and a plurality of thin-film layers stacked on top of each other above the substrate. The layers contain conductive patterns and vias that provide connections between the conductive pattern in one of the layers to the conductive pattern in another layer. Vias that provide a connection between the conductive pattern of one layer to the conductive pattern in another remotely located layer are offset and in contact with respect to each other and are positioned in a non-linear arrangement, preferably in the form of a helix or a multiple helix.
摘要翻译：描述了用于非平面结构的薄膜装置。该结构包括基板和层叠在基板上方的彼此顶部的多个薄膜层。这些层包含导电图案和通孔，其提供在一个层中的导电图案与另一层中的导电图案之间的连接。在另一个位于远的位置的层之间提供一层导电图案与导电图案之间的连接的通孔相对于彼此偏移并接触，并且以非线性排列方式定位，优选为螺旋形或多重螺旋

6. 发明授权

US4535467A Switch logic for shift register latch pair 失效
标题翻译：移位寄存器锁存器对的开关逻辑
公开(公告)号：US4535467A
公开(公告)日：1985-08-13
申请号：US445601
申请日：1982-11-30
申请人： James W. Davis , Joel C. Leininger , Carlos Munoz-Bustamante , Gordon J. Robbins
发明人： James W. Davis , Joel C. Leininger , Carlos Munoz-Bustamante , Gordon J. Robbins
IPC分类号： G01R31/28 , G01R31/3185 , H01L21/822 , H01L27/04 , H03K3/286 , H03K3/2885 , G11C19/00
CPC分类号： G01R31/318541 , H03K3/2885
摘要： A Level Sensitive Scan Design (LSSD) Shift Register Latch pair implemented in current switch logic is disclosed. The arrangement is characterized by the logic used to control the L1 and L2 latches being implemented in Differential Cascode Current Switch logic and the L1/L2 latches being coupled to only one current source. A "merged" L1/L2 latch arrangement employing only one current source is provided for an LSSD testing environment.
摘要翻译：液位敏感扫描设计（LSSD）移位寄存器公开了当前开关逻辑中实现的锁存器对。该装置的特征在于用于控制在差分串联电流开关逻辑中实现的L1和L2锁存器的逻辑，并且L1 / L2锁存器仅耦合到一个电流源。为LSSD测试环境提供了仅使用一个电流源的“合并”L1 / L2锁存装置。

7. 发明授权

US06457089B1 Microprocessor bus structure 失效
标题翻译：微处理器总线结构
公开(公告)号：US06457089B1
公开(公告)日：2002-09-24
申请号：US09422368
申请日：1999-10-21
申请人： Gordon J. Robbins , Donald Norman Senzig
发明人： Gordon J. Robbins , Donald Norman Senzig
IPC分类号： G06F1300
CPC分类号： G06F13/4217
摘要： The present invention discloses a microprocessor bus structure that enables a processor chip to be designed with optional unidirectional or bi-directional I/O buses. The processor is designed with separate input and output bus internal to the chip. A gating network is coupled to these processor uni-directional busses that allows the chip to have an alternate externally wired bus structure. For the lowest cost and lowest performance only one set of bidirectional bus lines are wired external to the chip. These lines have a parallel driver and receiver with appropriate gating to allow the bus to be either in the send or receive mode. The signals from the processor uni-directional input and output buses are wired via appropriate gating to create a single bi-directional bus. For high performance operation where higher cost for higher bandwidth is justified, the bidirectional bus is gated to be a device output only bus and the alternate device input bus is gated to the processor input bus creating a true uni-directional bus structure. The bus enable line is wired to the appropriated stated depending on the wired microprocessor bus structure.
摘要翻译：本发明公开了一种微处理器总线结构，其使处理器芯片能够被设计成具有可选的单向或双向I / O总线。处理器设计有独立的输入和输出总线内部的芯片。选通网络耦合到这些处理器单向总线，其允许芯片具有替代的外部有线总线结构。对于最低成本和最低性能，只有一组双向总线线路连接到芯片的外部。这些线路具有并行驱动器和接收器，具有适当的门控，以允许总线处于发送或接收模式。来自处理器单向输入和输出总线的信号通过适当的门控进行连接，以创建单个双向总线。对于高性能操作，为更高的带宽提供更高的成本，双向总线被门控为仅器件输出总线，并且备用器件输入总线选通处理器输入总线，从而创建一个真正的单向总线结构。总线使能线根据有线微处理器总线结构连接到适当的状态。

8. 发明授权

US6067633A Design and methodology for manufacturing data processing systems having multiple processors 失效
标题翻译：用于制造具有多个处理器的数据处理系统的设计和方法
公开(公告)号：US6067633A
公开(公告)日：2000-05-23
申请号：US52248
申请日：1998-03-31
申请人： Gordon J. Robbins , David Ray Bearden
发明人： Gordon J. Robbins , David Ray Bearden
IPC分类号： H01L21/822 , G06F11/00 , G06F15/78 , H01L23/538 , H01L27/04 , G06F11/22
CPC分类号： G06F11/2236 , H01L2224/16225 , H01L2924/00014
摘要： A multi-processor system and methodology optimize overhead costs associated with manufacturing large integrated circuit devices having multiple data processors and processing elements thereon by effectively disabling processing elements that are not functional. Disabling the processing elements is performed through segmented power distribution on an integrated circuit first-level package or by providing inhibit signals in pre-selected logic states based on the functionality of the multi-processing system. The functionality of the multiprocessing system is determined during an initial testing procedure, including wafer-level testing.
摘要翻译：多处理器系统和方法通过有效地禁用不起作用的处理元件来优化与制造具有多个数据处理器和处理元件的大型集成电路器件相关联的开销成本。通过集成电路第一级封装上的分段功率分配或基于多处理系统的功能提供预先选择的逻辑状态中的禁止信号来执行禁止处理元件。在初始测试过程中确定多处理系统的功能，包括晶圆级测试。

9. 发明授权

US5523619A High density memory structure 失效
标题翻译：高密度存储器结构
公开(公告)号：US5523619A
公开(公告)日：1996-06-04
申请号：US146845
申请日：1993-11-03
申请人： Michael F. McAllister , James A. McDonald , Gordon J. Robbins , Madhavan Swaminathan , Gregory M. Wilkins
发明人： Michael F. McAllister , James A. McDonald , Gordon J. Robbins , Madhavan Swaminathan , Gregory M. Wilkins
IPC分类号： H01L25/18 , G06F11/00 , G11C5/00 , H01L23/34 , H01L25/065 , H01L25/07 , H01L23/02
CPC分类号： H01L25/0657 , G06F11/00 , H01L23/34 , H01L23/642 , H01L2225/06527 , H01L2225/06551 , H01L2225/06589 , H01L25/18 , H01L2924/0002
摘要： A memory cube comprising a plurality of memory chips, each having a plurality of data storage devices, is provided with an auxiliary chip having inactive line termination circuits and the auxiliary chip or chips are formed as part of the memory cube structure and disposed among the memory chips on an interleave basis. The auxiliary circuit chips are provided with external terminals connected to memory input leads, control leads and data write leads, in close proximity to the termination point of the leads. A decoupling capacitor, integrated in the auxiliary circuit chip, is connected to the power bus in the memory cube structure and eliminates extraneous noise problems occurring with discrete capacitors external to the cube. A heating resistor is provided on the auxiliary circuit chip to maintain the cube structure at a near constant temperature. Temperature sensing diodes are incorporated in the auxiliary chip to provide an accurate mechanism for sensing the temperature internal to the cube.
摘要翻译：包括多个存储器芯片的存储器立方体，每个存储器芯片具有多个数据存储设备，其具有一个具有不活动的线路终端电路的辅助芯片，并且辅助芯片或芯片形成为存储器立方体结构的一部分并且被布置在存储器以交错为基础的芯片。辅助电路芯片设有外部端子，它们连接到与引线端接点接近的存储器输入引线，控制引线和数据写入引线。集成在辅助电路芯片中的去耦电容器连接到存储器立方体结构中的电源总线，并消除了立方体外部的离散电容器发生的外来噪声问题。在辅助电路芯片上设置加热电阻器，以将立方体结构保持在接近恒定的温度。温度感测二极管被并入辅助芯片中，以提供用于感测立方体内部温度的精确机构。

10. 发明授权

US5464682A Minimal capture pads applied to ceramic vias in ceramic substrates 失效
标题翻译：最小的捕获垫应用于陶瓷衬底中的陶瓷通孔
公开(公告)号：US5464682A
公开(公告)日：1995-11-07
申请号：US166424
申请日：1993-12-14
申请人： Eric D. Perfecto , Chandrika Prasad , Keshav Prasad , Gordon J. Robbins , Madhavan Swaminathan , George E. White
发明人： Eric D. Perfecto , Chandrika Prasad , Keshav Prasad , Gordon J. Robbins , Madhavan Swaminathan , George E. White
IPC分类号： H01L23/538 , H05K1/03 , H05K1/11 , H05K3/40 , H05K3/46 , B32B9/00
CPC分类号： H05K1/116 , H01L23/5384 , H01L23/5386 , H01L2224/16225 , H01L2924/15312 , H05K1/0306 , H05K1/113 , H05K1/115 , H05K2201/0367 , H05K3/4007 , H05K3/4611 , H05K3/4629 , H05K3/467 , Y10S428/901 , Y10T428/24926
摘要： A device includes a ceramic substrate. A ceramic via is defined within the ceramic substrate at an actual location which differs from a designed desired location for the ceramic via. A minimal capture pad electrically communicates the actual location with the designed desired location. The minimal capture pad contains a ceramic via contact portion, a thin film stud contact portion, and a connecting portion; and each of the three is configured to be as small as permitted to limit the capacitances produced by the capture pad.
摘要翻译：一种器件包括陶瓷衬底。在陶瓷衬底内的陶瓷通孔限定在不同于用于陶瓷通孔的设计的所需位置的实际位置。最小捕获垫将实际位置与设计的所需位置电连通。最小捕获垫包含陶瓷通孔接触部分，薄膜螺柱接触部分和连接部分; 并且三个中的每一个被配置为尽可能小以限制由捕获垫产生的电容。

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