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1. 发明授权

US08089768B2 Component arragement with an optimized assembly capability 有权
标题翻译：具有优化装配能力的组件装配
公开(公告)号：US08089768B2
公开(公告)日：2012-01-03
申请号：US11659297
申请日：2005-07-14
申请人： Anton Mauder , Wolfgang Scholz
发明人： Anton Mauder , Wolfgang Scholz
IPC分类号： H05K7/20 , H01L23/36
CPC分类号： G02B6/4494 , G02B6/441 , H01L2924/0002 , H05K3/325 , H05K2201/10409 , H05K2201/10689 , H05K2201/2036 , H01L2924/00
摘要： The invention relates to a component arrangement. In at least one embodiment, the component arrangement comprises: an electronics module; a heat sink contacted by the electronics module; a printed circuit board, and; a fastening means for fastening the electronics module to the printed circuit board and to the heat sink. The electronics module has at least one elastic connecting limb for the solder-free contacting of the electronics module with the printed circuit board and has a location for the fastening means. The electronics module additionally comprises a decoupling means for decoupling the force of pressure between the connecting limb and the printed circuit board from the contact force between the heat sink and the electronics module. In at least one embodiment of the invention an electronics module is provided that can be used in the aforementioned component arrangement.
摘要翻译：本发明涉及一种组件装置。在至少一个实施例中，组件布置包括：电子模块; 由电子模块接触的散热器; 印刷电路板，以及用于将电子模块紧固到印刷电路板和散热器的紧固装置。电子模块具有至少一个弹性连接臂，用于电子模块与印刷电路板的无焊料接触并且具有紧固装置的位置。电子模块还包括用于将连接肢和印刷电路板之间的压力与散热器和电子模块之间的接触力分离的去耦装置。在本发明的至少一个实施例中，提供了可以用于上述部件布置的电子模块。

2. 发明申请

US20090213552A1 Component arragement with an optimized assembly capability 有权
标题翻译：具有优化装配能力的组件装配
公开(公告)号：US20090213552A1
公开(公告)日：2009-08-27
申请号：US11659297
申请日：2005-07-14
申请人： Anton Mauder , Wolfgang Scholz
发明人： Anton Mauder , Wolfgang Scholz
IPC分类号： H05K7/20
CPC分类号： G02B6/4494 , G02B6/441 , H01L2924/0002 , H05K3/325 , H05K2201/10409 , H05K2201/10689 , H05K2201/2036 , H01L2924/00
摘要： The invention relates to a component arrangement comprising: an electronics module (10); a heat sink (20) contacted by the electronics module (10); a printed circuit board (30), and; a fastening means (40) for fastening the electronics module (10) to the printed circuit board (30) and to the heat sink (20). The electronics module (10) has at least one elastic connecting limb (11) for the solder-free contacting of the electronics module (10) with the printed circuit board (30) and has a location (14) for the fastening means (40). The electronics module (10) additionally comprises a decoupling means (12) for decoupling the force of pressure between the connecting limb (11) and the printed circuit board (30) from the contact force between the heat sink (20) and the electronics module (10). Another aspect of the invention concerns an electronics module (10) that can be used in the aforementioned component arrangement.
摘要翻译：本发明涉及一种组件装置，包括：电子模块（10）; 由所述电子模块（10）接触的散热器（20）; 印刷电路板（30），和用于将电子模块（10）紧固到印刷电路板（30）和散热器（20）的紧固装置（40）。电子模块（10）具有用于电子模块（10）与印刷电路板（30）的无焊料接触的至少一个弹性连接臂（11），并且具有用于紧固装置（40）的位置（14））。电子模块（10）还包括用于将连接臂（11）和印刷电路板（30）之间的压力与散热器（20）和电子模块（20）之间的接触力分离的解耦装置（12）（10）。本发明的另一方面涉及一种可用于上述组件布置的电子模块（10）。

3. 发明授权

US09245760B2 Methods of forming epitaxial layers on a porous semiconductor layer 有权
标题翻译：在多孔半导体层上形成外延层的方法
公开(公告)号：US09245760B2
公开(公告)日：2016-01-26
申请号：US12895664
申请日：2010-09-30
申请人： Anton Mauder , Hans-Joachim Schulze , Hans-Joerg Timme , Franz Hirler , Francisco Javier Santos Rodriguez
发明人： Anton Mauder , Hans-Joachim Schulze , Hans-Joerg Timme , Franz Hirler , Francisco Javier Santos Rodriguez
IPC分类号： H01L21/20 , H01L21/306 , H01L21/02 , H01L21/78 , H01L29/78
CPC分类号： H01L29/2003 , H01L21/0237 , H01L21/02381 , H01L21/0245 , H01L21/02513 , H01L21/02521 , H01L21/02532 , H01L21/0254 , H01L21/0262 , H01L21/306 , H01L21/30621 , H01L21/3065 , H01L21/324 , H01L21/78 , H01L29/045 , H01L29/45 , H01L29/7846 , H01L29/7848
摘要： In one embodiment, a method of forming a semiconductor device includes forming a first porous semiconductor layer over a top surface of a substrate. A first epitaxial layer is formed over the first porous semiconductor layer. A circuitry is formed within and over the first epitaxial layer. The circuitry is formed without completely oxidizing the first epitaxial layer.
摘要翻译：在一个实施例中，形成半导体器件的方法包括在衬底的顶表面上形成第一多孔半导体层。在第一多孔半导体层上形成第一外延层。在第一外延层内和上方形成电路。在不完全氧化第一外延层的情况下形成电路。

4. 发明授权

US08884360B2 Semiconductor device with improved robustness 有权
标题翻译：半导体器件具有改进的鲁棒性
公开(公告)号：US08884360B2
公开(公告)日：2014-11-11
申请号：US13404161
申请日：2012-02-24
申请人： Ralf Siemieniec , Oliver Blank , Anton Mauder , Franz Hirler
发明人： Ralf Siemieniec , Oliver Blank , Anton Mauder , Franz Hirler
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0623 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device includes a first contact in low Ohmic contact with a source region of the device and a first portion of a body region of the device formed in an active area of the device, and a second contact in low Ohmic contact with a second portion of the body region formed in a peripheral area of the device. The minimum width of the second contact at a first surface of the device is larger than the minimum width of the first contact at the first surface so that maximum current density during commutating the semiconductor device is reduced and thus the risk of device damage during hard commutating is also reduced.
摘要翻译：半导体器件包括与器件的源极区域的低欧姆接触的第一接触和形成在器件的有源区域中的器件的体区的第一部分，以及与第二部分的低欧姆接触的第二接触形成在装置的周边区域中的身体区域。器件第一表面处的第二触点的最小宽度大于第一表面处的第一接触的最小宽度，使得在半导体器件的整流期间的最大电流密度降低，并且因此在硬整流期间器件损坏的风险也减少了。

5. 发明授权

US08829584B2 Semiconductor device with a dynamic gate-drain capacitance 有权
标题翻译：具有动态栅极 - 漏极电容的半导体器件
公开(公告)号：US08829584B2
公开(公告)日：2014-09-09
申请号：US13614479
申请日：2012-09-13
申请人： Anton Mauder , Hans-Joachim Schulze , Carolin Tolksdorf , Winfried Kaindl , Armin Willmeroth
发明人： Anton Mauder , Hans-Joachim Schulze , Carolin Tolksdorf , Winfried Kaindl , Armin Willmeroth
IPC分类号： H01L27/07
CPC分类号： H01L27/0808 , H01L21/26513 , H01L27/0811 , H01L27/088 , H01L29/7836
摘要： A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.
摘要翻译：具有动态栅极漏极电容的半导体器件。一个实施例提供一种半导体器件。该器件包括半导体衬底，场效应晶体管结构，其包括源区，第一体区，漏区，栅电极结构和栅极绝缘层。栅极绝缘层设置在栅电极结构和体区之间。栅极电极结构和漏极区域部分地形成电容器结构，其包括栅极 - 漏极电容，该栅极 - 漏极电容被配置为随着施加在源极和漏极区域之间的变化的反向电压而动态地栅极 - 漏极电容在给定的阈值下包括至少一个局部最大值，或者在给定的反向电压下包括平台状过程。

6. 发明授权

US08822306B2 Method for manufacturing a composite wafer having a graphite core, and composite wafer having a graphite core 有权
标题翻译：具有石墨芯的复合晶片的制造方法以及具有石墨芯的复合晶片
公开(公告)号：US08822306B2
公开(公告)日：2014-09-02
申请号：US13206029
申请日：2011-08-09
申请人： Rudolf Berger , Hermann Gruber , Wolfgang Lehnert , Guenther Ruhl , Raimund Foerg , Anton Mauder , Hans-Joachim Schulze , Karsten Kellermann , Michael Sommer , Christian Rottmair , Roland Rupp
发明人： Rudolf Berger , Hermann Gruber , Wolfgang Lehnert , Guenther Ruhl , Raimund Foerg , Anton Mauder , Hans-Joachim Schulze , Karsten Kellermann , Michael Sommer , Christian Rottmair , Roland Rupp
IPC分类号： H01L21/30
CPC分类号： H01L21/76254 , C30B25/186 , H01L21/02115 , H01L21/02282 , H01L21/02598 , H01L21/2007 , H01L21/265 , H01L21/3212 , H01L21/324 , H01L21/76251 , H01L29/1608 , H01L29/20 , H01L29/2003
摘要： According to an embodiment, a composite wafer includes a carrier substrate having a graphite layer and a monocrystalline semiconductor layer attached to the carrier substrate.
摘要翻译：根据实施例，复合晶片包括具有石墨层和附着到载体衬底的单晶半导体层的载体衬底。

7. 发明申请

US20140042595A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING GRINDING FROM A BACK SURFACE AND SEMICONDUCTOR DEVICE 有权
标题翻译：制造包括从背面和半导体器件研磨的半导体器件的方法
公开(公告)号：US20140042595A1
公开(公告)日：2014-02-13
申请号：US13571769
申请日：2012-08-10
申请人： Hans-Joachim Schulze , Anton Mauder
发明人： Hans-Joachim Schulze , Anton Mauder
IPC分类号： H01L29/02 , H01L21/78
CPC分类号： H01L29/06 , B24B7/228 , B24B37/013 , B24B37/042 , H01L21/302 , H01L21/304 , H01L21/30625 , H01L21/3247 , H01L21/764 , H01L21/78 , H01L22/26 , H01L29/66333
摘要： A cavity is etched from a front surface into a semiconductor substrate. After providing an etch stop structure at the bottom of the cavity, the cavity is closed. From a back surface opposite to the front surface the semiconductor substrate is grinded at least up to an edge of the etch stop structure oriented to the back surface. Providing the etch stop structure at the bottom of an etched cavity allows for precisely adjusting a thickness of a semiconductor body of a semiconductor device.
摘要翻译：将腔从前表面刻蚀成半导体衬底。在腔的底部提供蚀刻停止结构之后，空腔被关闭。从与前表面相对的后表面，半导体衬底至少被研磨到定向到后表面的蚀刻停止结构的边缘。在蚀刻腔的底部提供蚀刻停止结构允许精确地调节半导体器件的半导体本体的厚度。

8. 发明申请

US20140001514A1 Semiconductor Device and Method for Producing a Doped Semiconductor Layer 审中-公开
标题翻译：用于制造掺杂半导体层的半导体器件和方法
公开(公告)号：US20140001514A1
公开(公告)日：2014-01-02
申请号：US13539944
申请日：2012-07-02
申请人： Hans-Joachim Schulze , Franz Hirler , Anton Mauder , Helmut Strack , Frank Kahlmann , Gerhard Miller
发明人： Hans-Joachim Schulze , Franz Hirler , Anton Mauder , Helmut Strack , Frank Kahlmann , Gerhard Miller
IPC分类号： H01L29/36 , H01L21/225
CPC分类号： H01L29/66348 , H01L21/2205 , H01L21/2658 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0878 , H01L29/102 , H01L29/1095 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/402 , H01L29/404 , H01L29/407 , H01L29/7397 , H01L29/7428 , H01L29/7802 , H01L29/7811 , H01L29/7813 , H01L29/7816 , H01L29/861 , H01L29/872
摘要： A semiconductor device includes a device region. The device region includes at least one device region section including dopant atoms of a first doping type and with a first doping concentration of at least 1E16 cm−3 and dopant atoms of a second doping type and with a second doping concentration of at least 1E16 cm−3.
摘要翻译：半导体器件包括器件区域。器件区域包括至少一个器件区域部分，其包括第一掺杂类型的掺杂剂原子和具有至少1E16cm-3的第一掺杂浓度和第二掺杂类型的掺杂剂原子，并且具有至少1E16cm的第二掺杂浓度 -3。

9. 发明申请

US20130341673A1 Reverse Conducting IGBT 审中-公开
标题翻译：反向导通IGBT
公开(公告)号：US20130341673A1
公开(公告)日：2013-12-26
申请号：US13529166
申请日：2012-06-21
申请人： Frank Pfirsch , Dorothea Werber , Anton Mauder , Carsten Schaeffer
发明人： Frank Pfirsch , Dorothea Werber , Anton Mauder , Carsten Schaeffer
IPC分类号： H01L29/739
CPC分类号： H03K17/127 , H01L29/0615 , H01L29/0619 , H01L29/0696 , H01L29/0834 , H01L29/404 , H01L29/407 , H01L29/7393 , H01L29/7395 , H01L29/7397 , H03K3/01 , H03K17/66
摘要： A semiconductor device includes a first emitter region of a first conductivity type, a second emitter region of a second conductivity type complementary to the first conductivity type, and a drift region of the second conductivity type arranged in a semiconductor body. The first and second emitter regions are arranged between the drift region and a first electrode and are each connected to the first electrode. A device cell of a cell region includes a body region of the first conductivity type adjoining the drift region, a source region of the second conductivity type adjoining the body region, and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric. A second electrode is electrically connected to the source region and the body region. A floating parasitic region of the first conductivity type is disposed outside the cell region.
摘要翻译：半导体器件包括第一导电类型的第一发射极区域，与第一导电类型互补的第二导电类型的第二发射极区域和布置在半导体本体中的第二导电类型的漂移区域。第一和第二发射极区域布置在漂移区域和第一电极之间并且各自连接到第一电极。单元区域的器件单元包括邻接漂移区的第一导电类型的主体区域，与身体区域邻接的第二导电类型的源极区域和与身体区域相邻并且与身体区域电介质绝缘的栅电极，栅极电介质。第二电极电连接到源区域和身体区域。第一导电类型的浮置寄生区域设置在单元区域的外部。

10. 发明授权

US08614478B2 Method for protecting a semiconductor device against degradation, a semiconductor device protected against hot charge carriers and a manufacturing method therefor 有权
标题翻译：防止半导体器件劣化的方法，保护热电荷载流子的半导体器件及其制造方法
公开(公告)号：US08614478B2
公开(公告)日：2013-12-24
申请号：US12843326
申请日：2010-07-26
申请人： Anton Mauder , Hans-Joachim Schulze
发明人： Anton Mauder , Hans-Joachim Schulze
IPC分类号： H01L29/66
CPC分类号： H01L29/407 , H01L21/283 , H01L29/063 , H01L29/0878 , H01L29/1608 , H01L29/2003 , H01L29/402 , H01L29/408 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/51 , H01L29/513 , H01L29/7393 , H01L29/7394 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L29/7835 , H01L29/792
摘要： A method for protecting a semiconductor device against degradation of its electrical characteristics is provided. The method includes providing a semiconductor device having a first semiconductor region and a charged dielectric layer which form a dielectric-semiconductor interface. The majority charge carriers of the first semiconductor region are of a first charge type. The charged dielectric layer includes fixed charges of the first charge type. The charge carrier density per area of the fixed charges is configured such that the charged dielectric layer is shielded against entrapment of hot majority charge carriers generated in the first semiconductor region. Further, a semiconductor device which is protected against hot charge carriers and a method for forming a semiconductor device are provided.
摘要翻译：提供了一种用于保护半导体器件免于其电特性劣化的方法。该方法包括提供具有形成介电半导体界面的第一半导体区域和带电介质层的半导体器件。第一半导体区域的多数电荷载流子是第一电荷类型。带电电介质层包括第一充电类型的固定电荷。固定电荷的每个面积的电荷载流子密度被配置为使得带电电介质层被屏蔽，以阻止在第一半导体区域中产生的热多数电荷载流子。此外，提供了防止热电荷载流子的半导体器件和形成半导体器件的方法。

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