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1. 发明授权

US5759046A Dendritic interconnection system 失效
标题翻译：树枝状互连系统
公开(公告)号：US5759046A
公开(公告)日：1998-06-02
申请号：US773922
申请日：1996-12-30
申请人： Anthony Paul Ingraham , Jaynal Abedin Molla , David Brian Stone
发明人： Anthony Paul Ingraham , Jaynal Abedin Molla , David Brian Stone
IPC分类号： H01R4/26 , H01R43/02 , H05K3/32 , H01R13/60
CPC分类号： H01R4/26 , H01R12/52 , H05K3/325 , H01R43/02
摘要： A technique of connecting a first member having a first face to a second member having a second face utilizing dendrites is provided. Dendrites are formed on one face of the first member in a given configuration. Dendrite receiving and securing material, preferably solder, is formed on a face of the second member in a configuration confirming substantially to the given configuration of the dendrites on the one face. The first and second members are then placed in a position relative to each other with the dendrites on the one face of the first member in contact with the dendrite receiving and engaging material on the face of the second member. An airtight seal is then provided between the first and second faces surrounding the dendrites and dendrite receiving and engaging material, which forms a sealed chamber between the first and second members. Thereafter, a vacuum is pulled within the sealed chamber, thereby causing the ambient air pressure on the two members to urge the two members toward each other which will embed the dendrites in the dendrite receiving and engaging material to form interconnection therebetween. In order to enhance or improve the bond between the dendrites and the dendrite receiving and securing material, the dendrites and dendrite receiving and securing material each contain a component which can form an intermetallic compound therebetween.
摘要翻译：提供了一种将具有第一面的第一构件与具有第二面的第二构件连接起来利用枝晶的技术。在给定的构造中，树枝状体形成在第一构件的一个面上。树枝状接收和固定材料（优选焊料）形成在第二构件的表面上，其构造基本上确认了在一个面上的树突的给定构型。然后将第一和第二构件相对于彼此放置在第一构件的一个面上的树突与第二构件的表面上的枝晶接收和接合材料接触的位置。然后在围绕树突和树枝状晶体接收和接合材料的第一和第二表面之间提供气密密封，其在第一和第二构件之间形成密封室。此后，在密封室内拉动真空，从而使两个构件上的环境空气压力相互推动两个构件，这两个构件将将树枝状物嵌入枝晶接收和接合材料中以在其间形成互连。为了增强或改善枝晶与树枝状晶体接收和固定材料之间的结合，枝晶和枝晶接收和固定材料各自含有可在其间形成金属间化合物的组分。

2. 发明授权

US6150255A Method of planarizing a curved substrate and resulting structure 失效
标题翻译：平面化弯曲基板和结构的方法
公开(公告)号：US6150255A
公开(公告)日：2000-11-21
申请号：US373868
申请日：1999-08-13
申请人： Francis Joseph Downes, Jr. , Stephen Joseph Fuerniss , Gary Ray Hill , Anthony Paul Ingraham , Voya Rista Markovich , Jaynal Abedin Molla
发明人： Francis Joseph Downes, Jr. , Stephen Joseph Fuerniss , Gary Ray Hill , Anthony Paul Ingraham , Voya Rista Markovich , Jaynal Abedin Molla
IPC分类号： H01L21/60 , H01L23/13 , H01L23/498 , H05K1/03 , H05K1/11 , H05K3/00 , H05K3/34 , H05K3/46 , H01L21/44
CPC分类号： H01L23/49833 , H01L23/13 , H01L24/16 , H01L24/81 , H01L24/83 , H01L24/90 , H01L2224/0401 , H01L2224/05557 , H01L2224/13099 , H01L2224/16225 , H01L2224/2919 , H01L2224/81052 , H01L2224/81191 , H01L2224/81385 , H01L2224/81801 , H01L2224/8319 , H01L2224/838 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01074 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/15174 , H01L2924/15312 , H01L2924/15787 , H05K1/0306 , H05K1/112 , H05K3/0023 , H05K3/3436 , H05K3/4644
摘要： According to the present invention a technique for providing a planarized substrate with dendritic connections of solder balls, especially a multi-layer ceramic substrate is provided. In the case where the substrate has a raised central portion on the top surface on which are disposed top surface metallurgy pads, a layer of conformable photoimagable material is placed over the top surface.The photoimagable material is exposed and developed in a pattern corresponding to the pattern of the top surface metallurgy pads to form vias in the photoimagable material. Copper is plated in the vias in contact with the top surface metallurgy pads. The exposed surface of the photoimagable surface is then planarized, preferably by mechanical polishing to form a flat planar surface, with the ends of the vias exposed. Dendritic connector pads are then grown on the exposed ends of the vias to which solder ball connections of an I/C chip are releasably connected.
摘要翻译：根据本发明，提供了一种用于为平坦化基板提供焊球，特别是多层陶瓷基板的树枝状连接的技术。在衬底在顶表面上具有凸起的中心部分的情况下，其上设置有顶表面冶金衬垫，一层适形的可光成像材料放置在顶表面上。可光成像材料以对应于顶表面冶金垫的图案的图案曝光和显影，以在可光成像材料中形成通孔。将铜镀在与顶部表面冶金垫接触的通孔中。然后将光致变形表面的暴露表面平坦化，优选通过机械抛光以形成平坦的平坦表面，其中通孔的端部暴露。然后，树枝状连接器焊盘在I / C芯片的焊球连接可释放地连接到的通孔的暴露端上生长。

3. 发明授权

US5994910A Apparatus, and corresponding method, for stress testing wire bond-type semi-conductor chips 失效
标题翻译：装置及相应的方法，用于应力测试导线接合型半导体芯片
公开(公告)号：US5994910A
公开(公告)日：1999-11-30
申请号：US160057
申请日：1998-09-24
申请人： Francis Joseph Downes, Jr. , Anthony Paul Ingraham , Jaynal Abedin Molla
发明人： Francis Joseph Downes, Jr. , Anthony Paul Ingraham , Jaynal Abedin Molla
IPC分类号： G01R31/28 , G01R1/073 , G01R31/02
CPC分类号： G01R31/2862
摘要： An apparatus, and a corresponding method, for stress-testing wire bond-type semiconductor chips is disclosed. The apparatus includes a clamp housing, with a spring-loaded screw extending through the top end of the housing. Contained within the clamp housing is a substantially rigid, electrically insulating base plate positioned at a lower end of the clamp housing. The upper surface of the base plate includes a depression which contains an insert fabricated either from an elastomeric material or a semiconductor material, such as silicon. A flexible, electrically insulating layer made from, for example, polyimide, overlies the base plate and insert. Significantly, the upper surface of the flexible, electrically insulating layer includes a plurality of dendritic contacts. It is through these dendritic contacts that electrical contact is made to the contact pads of a wire bond-type semiconductor chip.
摘要翻译：公开了一种用于应力测试引线接合型半导体芯片的装置和相应的方法。该装置包括夹紧壳体，其中弹簧加载的螺钉延伸穿过壳体的顶端。包含在夹具壳体内的是位于夹具壳体的下端的基本上刚性的电绝缘基板。基板的上表面包括凹陷，其包含由弹性体材料或诸如硅的半导体材料制成的插入件。由例如聚酰亚胺制成的柔性电绝缘层覆盖在基板和插入件上。重要的是，柔性电绝缘层的上表面包括多个树枝状接触。通过这些树突状触点，对引线接合型半导体芯片的接触焊盘进行电接触。

4. 发明授权

US5940729A Method of planarizing a curved substrate and resulting structure 失效
公开(公告)号：US5940729A
公开(公告)日：1999-08-17
申请号：US633984
申请日：1996-04-17
申请人： Francis Joseph Downes, Jr. , Stephen Joseph Fuerniss , Gary Ray Hill , Anthony Paul Ingraham , Voya Rista Markovich , Jaynal Abedin Molla
发明人： Francis Joseph Downes, Jr. , Stephen Joseph Fuerniss , Gary Ray Hill , Anthony Paul Ingraham , Voya Rista Markovich , Jaynal Abedin Molla
IPC分类号： H01L21/60 , H01L23/13 , H01L23/498 , H05K1/03 , H05K1/11 , H05K3/00 , H05K3/34 , H05K3/46 , H01L21/44
CPC分类号： H01L23/49833 , H01L23/13 , H01L24/16 , H01L24/81 , H01L24/83 , H01L24/90 , H01L2224/0401 , H01L2224/05557 , H01L2224/13099 , H01L2224/16225 , H01L2224/2919 , H01L2224/81052 , H01L2224/81191 , H01L2224/81385 , H01L2224/81801 , H01L2224/8319 , H01L2224/838 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01074 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/15174 , H01L2924/15312 , H01L2924/15787 , H05K1/0306 , H05K1/112 , H05K3/0023 , H05K3/3436 , H05K3/4644
摘要： According to the present invention a technique for providing a planarized substrate with dendritic connections of solder balls, especially a multi-layer ceramic substrate is provided. In the case where the substrate has a raised central portion on the top surface on which are disposed top surface metallurgy pads, a layer of conformable photoimagable material is placed over the top surface.The photoimagable material is exposed and developed in a pattern corresponding to the pattern of the top surface metallurgy pads to form vias in the photoimagable material. Copper is plated in the vias in contact with the top surface metallurgy pads. The exposed surface of the photoimagable surface is then planarized, preferably by mechanical polishing to form a flat planar surface, with the ends of the vias exposed. Dendritic connector pads are then grown on the exposed ends of the vias to which solder ball connections of an I/C chip are releasably connected.

5. 发明授权

US06414509B1 Method and apparatus for in-situ testing of integrated circuit chips 失效
标题翻译：用于集成电路芯片现场测试的方法和装置
公开(公告)号：US06414509B1
公开(公告)日：2002-07-02
申请号：US09564652
申请日：2000-05-03
申请人： Anilkumar Chinuprasad Bhatt , Leo Raymond Buda , Robert Douglas Edwards , Paul Joseph Hart , Anthony Paul Ingraham , Voya Rista Markovich , Jaynal Abedin Molla , Richard Gerald Murphy , George John Saxenmeyer, Jr. , George Frederick Walker , Bette Jaye Whalen , Richard Stuart Zarr
发明人： Anilkumar Chinuprasad Bhatt , Leo Raymond Buda , Robert Douglas Edwards , Paul Joseph Hart , Anthony Paul Ingraham , Voya Rista Markovich , Jaynal Abedin Molla , Richard Gerald Murphy , George John Saxenmeyer, Jr. , George Frederick Walker , Bette Jaye Whalen , Richard Stuart Zarr
IPC分类号： G01R3102
CPC分类号： H01L24/81 , G01R31/2886 , H01L22/20 , H01L24/75 , H01L2224/0401 , H01L2224/05557 , H01L2224/13111 , H01L2224/75 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A method of testing semiconductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip carrier is provided. The chip carrier has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into conductive contact with the conductor pads on the chip carrier. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing, the chip may be removed from the substrate. Alternatively, the chip may be bonded through the dendritic conductor pads to the substrate after successful testing.
摘要翻译：公开了半导体芯片的测试方法。单个半导体芯片具有I / O，电源和接地触点。在本发明的方法中，提供了一个芯片载体。芯片载体具有对应于半导体芯片上的触点的触点。载体触点具有树枝状表面。芯片触点与芯片载体上的导体焊盘导电接触。测试信号输入矢量被施加到半导体芯片的输入，从半导体芯片恢复输出信号矢量。在测试之后，芯片可以从衬底去除。或者，芯片可以在成功测试之后通过树枝状导体焊盘粘合到衬底上。

6. 发明授权

US06517698B1 System and method for providing rotation to plating flow 有权
标题翻译：提供旋转电镀流程的系统和方法
公开(公告)号：US06517698B1
公开(公告)日：2003-02-11
申请号：US09680871
申请日：2000-10-06
申请人： Timothy L. Johnson , Douglas G. Mitchell , Jaynal Abedin Molla
发明人： Timothy L. Johnson , Douglas G. Mitchell , Jaynal Abedin Molla
IPC分类号： C25D520
CPC分类号： C25D5/08 , C25D17/02 , C25D17/12
摘要： A system for electroplating integrated circuit wafers includes an electroplating solution containment chamber having a first end that is capable of supporting an integrated circuit wafer so that a surface of the wafer faces an internal volume of the chamber, and a second end opposing the first end across the internal volume. The system further includes a liquid directing element at the second end. The liquid directing element includes a plurality of channels having divergent axes so as to direct a helical flow of electroplating solution toward the surface of the integrated circuit wafer when the wafer is present and the liquid directing element is attached to a source of pressurized electroplating solution.
摘要翻译：一种用于电镀集成电路晶片的系统包括电镀溶液容纳室，该电镀溶液容纳室具有能够支撑集成电路晶片的第一端，使得晶片的表面面对腔室的内部容积，并且与第一端相对的第二端跨过内部音量。该系统还包括在第二端的液体引导元件。液体引导元件包括具有发散轴线的多个通道，以便当存在晶片时将电镀溶液的螺旋流引向集成电路晶片的表面，并将液体引导元件附接到加压电镀溶液源。

7. 发明授权

US06362089B1 Method for processing a semiconductor substrate having a copper surface disposed thereon and structure formed 有权
标题翻译：用于处理其上设置有铜表面并形成结构的半导体衬底的方法
公开(公告)号：US06362089B1
公开(公告)日：2002-03-26
申请号：US09294060
申请日：1999-04-19
申请人： Jaynal Abedin Molla , Owen Richard Fay
发明人： Jaynal Abedin Molla , Owen Richard Fay
IPC分类号： H01L2144
CPC分类号： H01L24/11 , H01L21/288 , H01L24/05 , H01L2224/0401 , H01L2224/05147 , H01L2224/05155 , H01L2224/05644 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01012 , H01L2924/01013 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , Y10T428/12528 , Y10T428/12875 , Y10T428/12903 , Y10T428/12944 , H01L2924/00014
摘要： A semiconductor wafer having copper bondpads (17) that are free of voids (13) and a method for coating the copper bondpads (17) with solderable or wirebondable metals such that the copper bondpads (17) are free of the voids (13). The void free metal coatings are achieved using a dual activation process. In a first activation step (27), the copper bondpads (17) are activated by placing them in a palladium bath. In a second activation step (28), the bondpads are placed in a nickel-boron bath. After the dual activation, the copper bondpads (17) are coated with a layer of nickel-phosphorous or palladium. The nickel-phosphorous or palladium layer may be coated with a layer of gold for subsequent formation of solder balls or wirebonds thereon.
摘要翻译：具有无空隙（13）的铜键合板（17）的半导体晶片以及用可焊接或引线键合的金属涂覆铜焊垫（17）的方法，使得铜键合垫（17）没有空隙（13）。使用双重活化方法实现无空隙金属涂层。在第一激活步骤（27）中，通过将铜粘合垫（17）放置在钯浴中来活化。在第二激活步骤（28）中，将粘合垫放置在镍 - 硼浴中。在双重激活之后，铜箔焊盘（17）涂覆有一层镍 - 磷或钯。镍 - 磷或钯层可以涂覆有一层金，用于随后在其上形成焊球或引线键。

8. 发明授权

US5939786A Uniform plating of dendrites 失效
标题翻译：树突的均匀电镀
公开(公告)号：US5939786A
公开(公告)日：1999-08-17
申请号：US748462
申请日：1996-11-08
申请人： Francis Joseph Downes, Jr. , Raymond Thomas Galasco , Jaynal Abedin Molla
发明人： Francis Joseph Downes, Jr. , Raymond Thomas Galasco , Jaynal Abedin Molla
IPC分类号： H01L21/48 , H01L23/498 , H05K3/40 , H01L23/48
CPC分类号： H01L23/49811 , H01L21/4853 , H05K3/4007 , H01L2924/0002 , H05K2201/09481 , H05K2203/0307 , H05K2203/0723 , Y10T29/49126 , Y10T29/49155
摘要： The present invention provides uniform dendrites, on circuit features instead of large, elongated dendrites along the edges of the circuit features. The dendrites are formed by a method comprising the following steps: providing a substrate having circuitry disposed thereon; applying a photoresist to the substrate at a thickness which is preferably about the height of the intended dendrite height; imaging the photoresist to expose all or a portion of the top surface of the circuitry; forming the dendrites; and removing the photoresist. The photoresist which is employed to control the dendrite height is applied so that the photoresist either: abuts the edge of the circuitry leaving the top surface of the circuitry exposed; or abuts the edge of the circuitry and extend over the top edge of the circuitry so that a portion of the top surface of the circuitry is exposed; or does not touch the circuitry nor an area surrounding the base of the circuitry. The method of the present invention provides uniform dendrites, that is, the dendrites along the edge of the circuitry are within about 50%, preferably about 40%, more preferably within about 25% of the average dendrite height; preferably the dendrites along the edge of the circuitry are within 10% of the highest non-edge dendrite. The invention also relates to electronic structures having uniform dendrites disposed thereon.
摘要翻译：本发明提供了均匀的枝晶，电路特征，而不是沿着电路特征边缘的大的细长的枝晶。树突通过包括以下步骤的方法形成：提供其上设置有电路的基板; 将光致抗蚀剂以优选约为预期枝晶高度的高度的厚度施加到基底上; 成像光致抗蚀剂以暴露电路的顶表面的全部或一部分; 形成枝晶; 并去除光致抗蚀剂。应用用于控制枝晶高度的光致抗蚀剂，使得光致抗蚀剂可以：离开电路的边缘，暴露电路的顶表面; 或邻接电路的边缘并且在电路的顶部边缘上延伸，使得电路的顶部表面的一部分被暴露; 或者不接触电路，也不接触电路底部周围的区域。本发明的方法提供均匀的枝晶，即沿着电路边缘的枝晶在平均枝晶高度的约50％，优选约40％，更优选约25％的范围内; 优选沿着电路边缘的枝晶在最高非边缘枝晶的10％以内。本发明还涉及其上布置有均匀树突的电子结构。

9. 发明授权

US5813870A Selectively filled adhesives for semiconductor chip interconnection and encapsulation 失效
标题翻译：用于半导体芯片互连和封装的选择性填充的粘合剂
公开(公告)号：US5813870A
公开(公告)日：1998-09-29
申请号：US678852
申请日：1996-07-12
申请人： Michael Anthony Gaynes , Jaynal Abedin Molla , Steven Paul Ostrander , Judith Marie Roldan , George John Saxenmeyer , George Frederick Walker
发明人： Michael Anthony Gaynes , Jaynal Abedin Molla , Steven Paul Ostrander , Judith Marie Roldan , George John Saxenmeyer , George Frederick Walker
IPC分类号： H01L23/32 , H01L21/60 , H01L21/68 , H01R4/58
CPC分类号： H01L21/6835 , H01L2221/68345 , H01L2224/81101 , H01L2924/0002
摘要： Dielectric adhesive film patterned with clusters of electrically conductive filaments that extend through the film thickness for providing electrical interconnection and encapsulation. The dielectric adhesive material is reworkable. The clusters are formed by selectively electroplating a noble metal at a high current density.
摘要翻译：电介质粘合膜，其图案化为导电细丝簇，其延伸穿过膜厚度以提供电互连和封装。电介质粘合剂材料是可再加工的。通过以高电流密度选择性地电镀贵金属来形成簇。

10. 发明授权

US6043150A Method for uniform plating of dendrites 失效
标题翻译：枝晶均匀电镀方法
公开(公告)号：US6043150A
公开(公告)日：2000-03-28
申请号：US304920
申请日：1999-05-04
申请人： Francis Joseph Downes, Jr. , Raymond Thomas Galasco , Jaynal Abedin Molla
发明人： Francis Joseph Downes, Jr. , Raymond Thomas Galasco , Jaynal Abedin Molla
IPC分类号： H01L21/48 , H01L23/498 , H05K3/40 , H05K3/36
CPC分类号： H01L23/49811 , H01L21/4853 , H05K3/4007 , H01L2924/0002 , H05K2201/09481 , H05K2203/0307 , H05K2203/0723 , Y10T29/49126 , Y10T29/49155
摘要： The present invention provides a novel method for forming uniform dendrites, on circuit features that does not result in large, elongated dendrites along the edges of the circuit features. The method comprises the following steps: providing a substrate having circuitry disposed thereon; applying a photoresist to the substrate at a thickness which is preferably about the height of the intended dendrite height; imaging the photoresist to expose all or a portion of the top surface of the circuitry; forming the dendrites; and removing the photoresist. The photoresist which is employed to control the dendrite height is applied so that the photoresist either: abuts the edge of the circuitry leaving the top surface of the circuitry exposed; or abuts the edge of the circuitry and extend over the top edge of the circuitry so that a portion of the top surface of the circuitry is exposed; or does not touch the circuitry nor an area surrounding the base of the circuitry. The method of the present invention provides uniform dendrites, that is, the dendrites along the edge of the circuitry are within about 50%, preferably about 40%, more preferably within about 25% of the average dendrite height; preferably the dendrites along the edge of the circuitry are within 10% of the highest non-edge dendrite. The invention also relates to electronic structures having uniform dendrites disposed thereon.
摘要翻译：本发明提供了一种用于形成均匀枝晶的新方法，其电路特征不会导致沿着电路特征边缘的大的细长树突。该方法包括以下步骤：提供其上设置有电路的基板; 将光致抗蚀剂以优选约为预期枝晶高度的高度的厚度施加到基底上; 成像光致抗蚀剂以暴露电路的顶表面的全部或一部分; 形成枝晶; 并去除光致抗蚀剂。应用用于控制枝晶高度的光致抗蚀剂，使得光致抗蚀剂可以：离开电路的边缘，暴露电路的顶表面; 或邻接电路的边缘并且在电路的顶部边缘上延伸，使得电路的顶部表面的一部分被暴露; 或者不接触电路，也不接触电路底部周围的区域。本发明的方法提供均匀的枝晶，即沿着电路边缘的枝晶在平均枝晶高度的约50％，优选约40％，更优选约25％的范围内; 优选沿着电路边缘的枝晶在最高非边缘枝晶的10％以内。本发明还涉及其上布置有均匀树突的电子结构。

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