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1. 发明授权

US5488646A Clock divider 失效
标题翻译：时钟分频器
公开(公告)号：US5488646A
公开(公告)日：1996-01-30
申请号：US409108
申请日：1995-03-23
申请人： Anthony M. Jones , David A. Barnes
发明人： Anthony M. Jones , David A. Barnes
IPC分类号： G06F1/08 , H03K5/15 , H03K21/02 , H03K3/78 , H03K21/10
CPC分类号： H03K5/15026 , G06F1/08
摘要： The invention discloses a method and an apparatus for implementing an L phase clock in conjuction with L counters, where L is an integer, to count at a frequency scalable by L.
摘要翻译：本发明公开了一种与L个计数器结合实现L相时钟的方法和装置，其中L为整数，以L为可调整的频率进行计数。

2. 发明授权

US5617458A Clock divider 失效
标题翻译：时钟分频器
公开(公告)号：US5617458A
公开(公告)日：1997-04-01
申请号：US567555
申请日：1995-12-05
申请人： Anthony M. Jones , David A. Barnes
发明人： Anthony M. Jones , David A. Barnes
IPC分类号： G06F1/08 , H03K5/15 , H03H11/26
CPC分类号： H03K5/15026 , G06F1/08
摘要： The invention discloses a method and an apparatus for implementing an L phase clock in conjuction with L counters, where L is an integer, to count at a frequency scalable by L.
摘要翻译：本发明公开了一种与L个计数器结合实现L相时钟的方法和装置，其中L是一个整数，以L可缩放的频率进行计数。

3. 发明授权

US5635864A Comparator circuit 失效
标题翻译：比较器电路
公开(公告)号：US5635864A
公开(公告)日：1997-06-03
申请号：US480997
申请日：1995-06-07
申请人： Anthony M. Jones
发明人： Anthony M. Jones
IPC分类号： H04N7/26 , H03H17/02 , H03H21/00 , H03K5/24 , H03M3/02 , H03M13/00 , H03M13/15 , H03M13/27 , H04B3/06 , H04L1/00 , H04L7/00 , H04L7/033 , H04L7/04 , H04L25/03 , H04L25/06 , H04L27/00 , H04L27/02 , H04L27/06 , H04L27/227 , H04L27/38 , H04N5/00 , H04N5/21 , H04N5/44 , H04N5/455 , H04N5/52 , H04N7/24 , H04N7/30 , H04N21/2383 , H04N21/438 , H03K5/22 , H03K5/153
CPC分类号： H04L1/0057 , H03K5/24 , H03M13/15 , H03M13/151 , H03M13/2707 , H03M13/2764 , H04L1/0045 , H04L1/0071 , H04L25/03038 , H04L25/03866 , H04L25/062 , H04L27/02 , H04L27/2273 , H04L27/3809 , H04N5/211 , H04N5/4401 , H04N5/4446 , H04N5/455 , H04N5/52 , H04L2027/0032 , H04L2027/0061 , H04L2027/0067 , H04L2027/0073 , H04L2027/0081 , H04L7/0334
摘要： A high speed analog-to-digital converter employs a comparator having first and second units cross coupled in a positive feedback loop. The units are alternately connected to an input voltage and a reference voltage, after which positive feedback is introduced established, and a differential output established. The arrangement is fully symmetric, and balanced and rejects common-mode switching noise.
摘要翻译：高速模数转换器采用具有在正反馈回路中交叉耦合的第一和第二单元的比较器。这些单元交替地连接到输入电压和参考电压，之后建立正反馈并建立差分输出。该布置是完全对称的，平衡的并且拒绝共模开关噪声。

4. 发明授权

US5479364A Method and arrangement for transformation of signals from a frequency to a time domain 失效
标题翻译：信号从频率变换到时域的方法和装置
公开(公告)号：US5479364A
公开(公告)日：1995-12-26
申请号：US82087
申请日：1993-06-24
申请人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
发明人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
IPC分类号： H04N1/41 , G06F17/14 , G06T1/20 , H04N7/30 , G06F7/38
CPC分类号： G06F17/147
摘要： An IDCT, or Inverse Discrete Cosine Transform, method decimates a 2-D IDCT into two 1-D IDCT operations and then operates separately on the even and odd pixel input words. In a common processing step, selected input values are passed directly to output adders and subtractors, while others are multiplied by constant, scaled cosine values. In a pre-common processing step, the lowest-order odd input word is pre-multiplied by .sqroot.2, and the odd input words are summed pairwise before processing in a common processing step. In a post-common processing step, intermediate values corresponding to the processed odd input words are multiplied by predetermined coefficients to form odd resultant values. After calculation of the even and odd resultant values, the high-order and low-order outputs are formed by simple subtraction/addition, respectively, of the odd resultant values from/with the even resultant values. The input values are preferably scaled upward by a factor of .sqroot.2. Selected bits of some intermediate resulting data words are optionally adjusted by forcing these bits to either "1" or "0". The IDCT system includes a pre-common processing circuit (PREC), a common processing circuit (CBLK), and a post-common processing circuit (POSTC), which perform the necessary operations in the respective steps. The system also includes a controller (CNTL) to generate signals to control the loading of system latches and, preferably, to time-multiplex the application of the even and odd input words to latches in the pre-common circuit.
摘要翻译： IDCT或逆离散余弦变换方法将2-D IDCT分解成两个1-D IDCT操作，然后分别对偶数和奇数像素输入字进行操作。在通常的处理步骤中，所选择的输入值直接传递到输出加法器和减法器，而其他输入值乘以恒定的缩放余弦值。在预共同处理步骤中，最低阶奇数输入字被预先乘以2ROOT 2，并且奇数输入字在公共处理步骤中处理之前成对加法。在公知处理步骤中，将与处理的奇数输入字对应的中间值乘以预定系数，以形成奇数合成值。在偶数和奇数结果值的计算之后，高次和低阶输出分别由奇偶结果值/偶数结果值的简单减法/加法形成。输入值优选地向上按比例2ROOT 2.通过将这些位强制为“1”或“0”可选地调整某些中间结果数据字的选定位。 IDCT系统包括在各步骤中执行必要操作的预共同处理电路（PREC），公共处理电路（CBLK）和后公共处理电路（POSTC）。该系统还包括用于产生信号以控制系统锁存器的加载的控制器（CNTL），并且优选地将偶数和奇数输入字的应用时间复用到预共同电路中的锁存器。

5. 发明授权

US07408519B2 Dual polarization antenna array with inter-element capacitive coupling plate and associated methods 失效
标题翻译：双极化天线阵列与元件间电容耦合板及相关方法
公开(公告)号：US07408519B2
公开(公告)日：2008-08-05
申请号：US11303342
申请日：2005-12-16
申请人： Timothy E. Durham , Anthony M. Jones , Griffin K. Gothard , Sean Ortiz
发明人： Timothy E. Durham , Anthony M. Jones , Griffin K. Gothard , Sean Ortiz
IPC分类号： H01Q13/10
CPC分类号： H01Q21/065 , H01Q1/38 , H01Q21/26
摘要： The dual-polarization antenna with a slot pattern can produce vertical polarized energy near the horizon and can scan to near grazing angles. The dual-polarization, slot-mode antenna includes an array of dual-polarization, slot-mode, antenna units carried by a substrate, and each dual-polarization, slot-mode antenna unit having at least four patch antenna elements arranged in spaced apart relation about a central feed position. Adjacent patch antenna elements of adjacent dual-polarization, slot-mode antenna units have respective spaced apart edge portions defining gaps therebetween. Capacitive coupling plates are adjacent the gaps and overlap the respective spaced apart edge portions to provide increased capacitive coupling therebetween.
摘要翻译：具有槽纹图案的双极化天线可以在水平线附近产生垂直极化能量，并且可以扫描到接近的掠角。双极化时隙模式天线包括由衬底承载的双极化，时隙模式天线单元的阵列，并且每个双极化时隙模式天线单元具有间隔布置的至少四个贴片天线元件关于中央进给位置的关系。相邻双极化缝隙天线单元的相邻贴片天线元件具有限定间隙的相应间隔开的边缘部分。电容耦合板与间隙相邻并且与相应的间隔开的边缘部分重叠，以在它们之间提供增加的电容耦合。

6. 发明授权

US07221322B1 Dual polarization antenna array with inter-element coupling and associated methods 失效
标题翻译：具有元件间耦合和相关方法的双极化天线阵列
公开(公告)号：US07221322B1
公开(公告)日：2007-05-22
申请号：US11303712
申请日：2005-12-14
申请人： Timothy E. Durham , Anthony M. Jones , Griffin K. Gothard , Sean Ortiz
发明人： Timothy E. Durham , Anthony M. Jones , Griffin K. Gothard , Sean Ortiz
IPC分类号： H01Q1/38
CPC分类号： H01Q21/065 , H01Q1/38 , H01Q21/26
摘要： The dual-polarization, slot-mode antenna includes an array of dual-polarization, slot-mode, antenna units carried by a substrate, with each dual-polarization, slot-mode antenna unit having at least four patch antenna elements arranged in spaced apart relation about a central feed position. Adjacent patch antenna elements of adjacent dual-polarization, slot-mode antenna units include respective spaced apart edge portions having predetermined shapes and relative positioning to provide increased capacitive coupling therebetween. The respective spaced apart edge portions may be continuously or periodically interdigitated to provide the increased capacitive coupling therebetween.
摘要翻译：双极化时隙模式天线包括由衬底承载的双偏振时隙模式天线单元的阵列，每个双极化缝隙模式天线单元具有间隔布置的至少四个贴片天线元件关于中央进给位置的关系。相邻双极化缝隙天线单元的相邻贴片天线单元包括具有预定形状和相对定位的相应间隔开的边缘部分，以在它们之间提供增加的电容耦合。相应的间隔开的边缘部分可以连续地或周期性地交错，以在它们之间提供增加的电容耦合。

7. 发明授权

US5590067A Method and arrangement for transformation of signals from a frequency to a time domain 失效
标题翻译：信号从频率变换到时域的方法和装置
公开(公告)号：US5590067A
公开(公告)日：1996-12-31
申请号：US404067
申请日：1995-03-14
申请人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
发明人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
IPC分类号： H04N1/41 , G06F17/14 , G06T1/20 , H04N7/30 , G06F7/38
CPC分类号： G06F17/147
摘要： An IDCT method decimates a 2-D IDCT into two 1-D IDCT operations and then operates separately on the even and odd pixel input words. In a common processing step, selected input values are passed directly to output adders and subtractors, while others are multiplied by constant, scaled cosine values. In a pre-common processing step, the lowest-order odd input word is pre-multiplied by .sqroot. 2, and the odd input words are summed pairwise before processing in a common processing step. In a post-common processing step, intermediate values corresponding to the processed odd input words are multiplied by predetermined coefficients to form odd resultant values. After calculation of the even and odd resultant values, the high-order and low-order outputs are formed by simple subtraction/addition, respectively, of the odd resultant values from/with the even resultant values. The input values are preferably scaled upward by a factor of .sqroot. 2. Selected bits of some intermediate resulting data words are optionally adjusted by forcing these bits to either "1" or "0". The IDCT system includes a pre-common processing circuit (PREC), a common processing circuit (CBLK), and a post-common processing circuit (POSTC), which perform the necessary operations in the respective steps. The system also includes a controller (CNTL) to generate signals to control the loading of system latches and, preferably, to time-multiplex the application of the even and odd input words to latches in the pre-common circuit.
摘要翻译： IDCT方法将2-D IDCT分解成两个1-D IDCT操作，然后分别对偶数和奇数像素输入字进行操作。在通常的处理步骤中，所选择的输入值直接传递到输出加法器和减法器，而其他输入值乘以恒定的缩放余弦值。在预共同处理步骤中，最低阶奇数输入字被预先乘以2ROOT + E，rad + EE 2，并且奇数输入字在公共处理步骤中处理之前成对相加。在公知处理步骤中，将与处理的奇数输入字对应的中间值乘以预定系数，以形成奇数合成值。在偶数和奇数结果值的计算之后，高次和低阶输出分别由奇偶结果值/偶数结果值的简单减法/加法形成。输入值优选地按照2ROOT + E，rad + EE2的因子向上扩展。通过将这些位强制为“1”或“0”，可选地调整一些中间结果数据字的选定位。 IDCT系统包括在各步骤中执行必要操作的预共同处理电路（PREC），公共处理电路（CBLK）和后公共处理电路（POSTC）。该系统还包括用于产生信号以控制系统锁存器的加载的控制器（CNTL），并且优选地将偶数和奇数输入字的应用时间复用到预共同电路中的锁存器。

8. 发明授权

US06956532B2 Multiband radially distributed phased array antenna with a stepped ground plane and associated methods 失效
标题翻译：多频带径向分布式相控阵天线，具有阶梯式接地平面及相关方法
公开(公告)号：US06956532B2
公开(公告)日：2005-10-18
申请号：US10702853
申请日：2003-11-06
申请人： Timothy E. Durham , Mark Vanstrum , Anthony M. Jones , Griffin K. Gothard
发明人： Timothy E. Durham , Mark Vanstrum , Anthony M. Jones , Griffin K. Gothard
IPC分类号： H01Q1/38 , H01Q3/24 , H01Q3/26 , H01Q3/30 , H01Q5/00 , H01Q5/40 , H01Q9/28 , H01Q19/10 , H01Q21/06 , H01Q21/00 , H01Q1/00
CPC分类号： H01Q21/065 , H01Q1/38 , H01Q3/247 , H01Q3/26 , H01Q3/30 , H01Q5/40 , H01Q9/285 , H01Q19/10
摘要： A multiband phased array antenna includes a substrate, and dipole element arrays extending outwardly from an imaginary center point on the substrate. Each dipole element array includes dipole antenna elements arranged in end-to-end relation and having a dipole size different than a dipole size of dipole antenna elements of at least one other dipole element array. A ground plane is adjacent the dipole element arrays, and a spacing between the dipole element arrays and the ground plane is different between the dipole element arrays having different size dipole antenna elements. The ground plane has a plateau shape for providing the different spacing between the dipole element arrays.
摘要翻译：多频带相控阵天线包括基板和从基板上的假想中心点向外延伸的偶极子阵列。每个偶极元件阵列包括以端对端关系布置的偶极天线元件，并且具有与至少一个其它偶极子元件阵列的偶极子天线元件的偶极子尺寸不同的偶极尺寸。接地平面与偶极元件阵列相邻，偶极元件阵列和接地平面之间的间隔在具有不同尺寸偶极子天线元件的偶极子元件阵列之间是不同的。接地平面具有平台形状，用于提供偶极子元件阵列之间的不同间隔。

9. 发明授权

US06943748B2 Multiband polygonally distributed phased array antenna and associated methods 有权
标题翻译：多频带多相分布相控阵天线及相关方法
公开(公告)号：US06943748B2
公开(公告)日：2005-09-13
申请号：US10703132
申请日：2003-11-06
申请人： Timothy E. Durham , Griffin K. Gothard , Anthony M. Jones
发明人： Timothy E. Durham , Griffin K. Gothard , Anthony M. Jones
IPC分类号： H01Q1/38 , H01Q3/24 , H01Q3/26 , H01Q3/30 , H01Q5/00 , H01Q5/40 , H01Q9/28 , H01Q19/10 , H01Q21/06 , H01Q21/26 , H01Q13/00 , H01Q1/48
CPC分类号： H01Q9/14 , H01Q1/38 , H01Q3/247 , H01Q3/26 , H01Q3/30 , H01Q5/40 , H01Q9/285 , H01Q19/10 , H01Q21/062
摘要： A phased array antenna includes a substrate, and dipole element arrays extending in concentric rings about an imaginary center point on the substrate. Each dipole element array includes dipole antenna elements arranged in an end-to-end relation and having a dipole size different than a dipole size of dipole antenna elements of at least one other dipole element array. A ground plane is adjacent the dipole element arrays, and a spacing between the dipole element arrays and the ground plane is different between the dipole element arrays having different size dipole antenna elements.
摘要翻译：相控阵天线包括基板和偶极子元件阵列，其围绕基板上的假想中心点以同心环延伸。每个偶极元件阵列包括以端对端关系布置的偶极天线元件，并且具有与至少一个其它偶极子元件阵列的偶极子天线元件的偶极子尺寸不同的偶极子尺寸。接地平面与偶极元件阵列相邻，偶极元件阵列和接地平面之间的间隔在具有不同尺寸偶极子天线元件的偶极子元件阵列之间是不同的。

10. 发明授权

US06894655B1 Phased array antenna with selective capacitive coupling and associated methods 失效
标题翻译：具有选择性电容耦合和相关方法的相控阵天线
公开(公告)号：US06894655B1
公开(公告)日：2005-05-17
申请号：US10702713
申请日：2003-11-06
申请人： Anthony M. Jones , Griffin K. Gothard , Timothy E. Durham , Jay Kralovec
发明人： Anthony M. Jones , Griffin K. Gothard , Timothy E. Durham , Jay Kralovec
IPC分类号： H01Q1/28 , H01Q1/50 , H01Q9/28 , H01Q21/00 , H01Q21/26
CPC分类号： H01Q21/062 , H01Q1/28 , H01Q5/42 , H01Q5/48
摘要： A phased array antenna includes a substrate, and an array of dipole antenna elements on the substrate. Each dipole antenna element includes a medial feed portion, and a pair of legs extending outwardly therefrom. Pairs of adjacent legs of adjacent dipole antenna elements include respective spaced apart end portions. The phased array antenna further includes selectable impedance elements and switches. Each switch is for selectively coupling at least one impedance element between a respective pair of adjacent legs of adjacent dipole antenna elements for changing the capacitive coupling therebetween.
摘要翻译：相控阵天线包括衬底和衬底上的偶极天线元件阵列。每个偶极天线元件包括中间馈送部分和从其向外延伸的一对腿。相邻偶极子天线元件的相邻支腿的对包括相应的间隔开的端部。相控阵天线还包括可选择的阻抗元件和开关。每个开关用于选择性地将至少一个阻抗元件耦合在相邻偶极子天线元件的相应的一对相邻的支腿之间，以改变它们之间的电容耦合。

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