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1. 发明授权

US5479364A Method and arrangement for transformation of signals from a frequency to a time domain 失效
标题翻译：信号从频率变换到时域的方法和装置
公开(公告)号：US5479364A
公开(公告)日：1995-12-26
申请号：US82087
申请日：1993-06-24
申请人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
发明人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
IPC分类号： H04N1/41 , G06F17/14 , G06T1/20 , H04N7/30 , G06F7/38
CPC分类号： G06F17/147
摘要： An IDCT, or Inverse Discrete Cosine Transform, method decimates a 2-D IDCT into two 1-D IDCT operations and then operates separately on the even and odd pixel input words. In a common processing step, selected input values are passed directly to output adders and subtractors, while others are multiplied by constant, scaled cosine values. In a pre-common processing step, the lowest-order odd input word is pre-multiplied by .sqroot.2, and the odd input words are summed pairwise before processing in a common processing step. In a post-common processing step, intermediate values corresponding to the processed odd input words are multiplied by predetermined coefficients to form odd resultant values. After calculation of the even and odd resultant values, the high-order and low-order outputs are formed by simple subtraction/addition, respectively, of the odd resultant values from/with the even resultant values. The input values are preferably scaled upward by a factor of .sqroot.2. Selected bits of some intermediate resulting data words are optionally adjusted by forcing these bits to either "1" or "0". The IDCT system includes a pre-common processing circuit (PREC), a common processing circuit (CBLK), and a post-common processing circuit (POSTC), which perform the necessary operations in the respective steps. The system also includes a controller (CNTL) to generate signals to control the loading of system latches and, preferably, to time-multiplex the application of the even and odd input words to latches in the pre-common circuit.
摘要翻译： IDCT或逆离散余弦变换方法将2-D IDCT分解成两个1-D IDCT操作，然后分别对偶数和奇数像素输入字进行操作。在通常的处理步骤中，所选择的输入值直接传递到输出加法器和减法器，而其他输入值乘以恒定的缩放余弦值。在预共同处理步骤中，最低阶奇数输入字被预先乘以2ROOT 2，并且奇数输入字在公共处理步骤中处理之前成对加法。在公知处理步骤中，将与处理的奇数输入字对应的中间值乘以预定系数，以形成奇数合成值。在偶数和奇数结果值的计算之后，高次和低阶输出分别由奇偶结果值/偶数结果值的简单减法/加法形成。输入值优选地向上按比例2ROOT 2.通过将这些位强制为“1”或“0”可选地调整某些中间结果数据字的选定位。 IDCT系统包括在各步骤中执行必要操作的预共同处理电路（PREC），公共处理电路（CBLK）和后公共处理电路（POSTC）。该系统还包括用于产生信号以控制系统锁存器的加载的控制器（CNTL），并且优选地将偶数和奇数输入字的应用时间复用到预共同电路中的锁存器。

2. 发明授权

US5590067A Method and arrangement for transformation of signals from a frequency to a time domain 失效
标题翻译：信号从频率变换到时域的方法和装置
公开(公告)号：US5590067A
公开(公告)日：1996-12-31
申请号：US404067
申请日：1995-03-14
申请人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
发明人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
IPC分类号： H04N1/41 , G06F17/14 , G06T1/20 , H04N7/30 , G06F7/38
CPC分类号： G06F17/147
摘要： An IDCT method decimates a 2-D IDCT into two 1-D IDCT operations and then operates separately on the even and odd pixel input words. In a common processing step, selected input values are passed directly to output adders and subtractors, while others are multiplied by constant, scaled cosine values. In a pre-common processing step, the lowest-order odd input word is pre-multiplied by .sqroot. 2, and the odd input words are summed pairwise before processing in a common processing step. In a post-common processing step, intermediate values corresponding to the processed odd input words are multiplied by predetermined coefficients to form odd resultant values. After calculation of the even and odd resultant values, the high-order and low-order outputs are formed by simple subtraction/addition, respectively, of the odd resultant values from/with the even resultant values. The input values are preferably scaled upward by a factor of .sqroot. 2. Selected bits of some intermediate resulting data words are optionally adjusted by forcing these bits to either "1" or "0". The IDCT system includes a pre-common processing circuit (PREC), a common processing circuit (CBLK), and a post-common processing circuit (POSTC), which perform the necessary operations in the respective steps. The system also includes a controller (CNTL) to generate signals to control the loading of system latches and, preferably, to time-multiplex the application of the even and odd input words to latches in the pre-common circuit.
摘要翻译： IDCT方法将2-D IDCT分解成两个1-D IDCT操作，然后分别对偶数和奇数像素输入字进行操作。在通常的处理步骤中，所选择的输入值直接传递到输出加法器和减法器，而其他输入值乘以恒定的缩放余弦值。在预共同处理步骤中，最低阶奇数输入字被预先乘以2ROOT + E，rad + EE 2，并且奇数输入字在公共处理步骤中处理之前成对相加。在公知处理步骤中，将与处理的奇数输入字对应的中间值乘以预定系数，以形成奇数合成值。在偶数和奇数结果值的计算之后，高次和低阶输出分别由奇偶结果值/偶数结果值的简单减法/加法形成。输入值优选地按照2ROOT + E，rad + EE2的因子向上扩展。通过将这些位强制为“1”或“0”，可选地调整一些中间结果数据字的选定位。 IDCT系统包括在各步骤中执行必要操作的预共同处理电路（PREC），公共处理电路（CBLK）和后公共处理电路（POSTC）。该系统还包括用于产生信号以控制系统锁存器的加载的控制器（CNTL），并且优选地将偶数和奇数输入字的应用时间复用到预共同电路中的锁存器。

3. 发明授权

US5596517A Method and arrangement for transformation of signals from a frequency to a time domain 失效
公开(公告)号：US5596517A
公开(公告)日：1997-01-21
申请号：US400722
申请日：1995-03-07
申请人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
发明人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
IPC分类号： H04N1/41 , G06F17/14 , G06T1/20 , H04N7/30 , G06F7/38
CPC分类号： G06F17/147
摘要： An IDCT, or Inverse Discrete Cosine Transform, method decimates a 2-D IDCT into two 1-D IDCT operations and then operates separately on the even and odd pixel input words. In a common processing step, selected input values are passed directly to output adders and subtractors, while others are multiplied by constant, scaled cosine values. In a pre-common processing step, the lowest-order odd input word is pre-multiplied by .sqroot.2, and the odd input words are summed pairwise before processing in a common processing step. In a post-common processing step, intermediate values corresponding to the processed odd input words are multiplied by predetermined coefficients to form odd resultant values. After calculation of the even and odd resultant values, the high-order and low-order outputs are formed by simple subtraction/addition, respectively, of the odd resultant values from/with the even resultant values. The input values are preferably scaled upward by a factor of .sqroot.2. Selected bits of some intermediate resulting data words are optionally adjusted by forcing these bits to either "1" or "0". The IDCT system includes a pre-common processing circuit (PREC), a common processing circuit (CBLK), and a post-common processing circuit (POSTC), which perform the necessary operations in the respective steps. The system also includes a controller (CNTL) to generate signals to control the loading of system latches and, preferably, to time-multiplex the application of the even and odd input words to latches in the pre-common circuit.

4. 发明授权

US5594678A Method and arrangement for transformation of signals from a frequency to a time domain 失效
标题翻译：信号从频率变换到时域的方法和装置
公开(公告)号：US5594678A
公开(公告)日：1997-01-14
申请号：US400723
申请日：1995-03-07
申请人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
发明人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
IPC分类号： H04N1/41 , G06F17/14 , G06T1/20 , H04N7/30 , G06F7/38
CPC分类号： G06F17/147
摘要： An IDCT, or Inverse Discrete Cosine Transform, method decimates a 2-D IDCT into two 1-D IDCT operations and then operates separately on the even and odd pixel input words. In a common processing step, selected input values are passed directly to output adders and subtractors, while others are multiplied by constant, scaled cosine values. In a pre-common processing step, the lowest-order odd input word is pre-multiplied by .sqroot.2, and the odd input words are summed pairwise before processing in a common processing step. In a post-common processing step, intermediate values corresponding to the processed odd input words are multiplied by predetermined coefficients to form odd resultant values. After calculation of the even and odd resultant values, the high-order and low-order outputs are formed by simple subtraction/addition, respectively, of the odd resultant values from/with the even resultant values. The input values are preferably scaled upward by a factor of .sqroot.2. Selected bits of some intermediate resulting data words are optionally adjusted by forcing these bits to either "1" or "0". The IDCT system includes a pre-common processing circuit (PREC), a common processing circuit (CBLK), and a post-common processing circuit (POSTC), which perform the necessary operations in the respective steps. The system also includes a controller (CNTL) to generate signals to control the loading of system latches and, preferably, to time-multiplex the application of the even and odd input words to latches in the pre-common circuit.
摘要翻译： IDCT或逆离散余弦变换方法将2-D IDCT分解成两个1-D IDCT操作，然后分别对偶数和奇数像素输入字进行操作。在通常的处理步骤中，所选择的输入值直接传递到输出加法器和减法器，而其他输入值乘以恒定的缩放余弦值。在预共同处理步骤中，最低阶奇数输入字被预先乘以2ROOT + E，rad 2 + EE，并且奇数输入字在公共处理步骤中处理之前成对地相加。在公知处理步骤中，将与处理的奇数输入字对应的中间值乘以预定系数，以形成奇数合成值。在偶数和奇数结果值的计算之后，高次和低阶输出分别由奇偶结果值/偶数结果值的简单减法/加法形成。输入值优选地向上扩展2ROOT + E，rad 2 + EE的因子。通过强制这些位为“1”或“0”可选地调整一些中间结果数据字的选定位。 IDCT系统包括在各步骤中执行必要操作的预共同处理电路（PREC），公共处理电路（CBLK）和后公共处理电路（POSTC）。该系统还包括用于产生信号以控制系统锁存器的加载的控制器（CNTL），并且优选地将偶数和奇数输入字的应用时间复用到预共同电路中的锁存器。

5. 发明授权

US5963154A Technique for decoding variable and fixed length codes 失效
标题翻译：解码变量和固定长度代码的技术
公开(公告)号：US5963154A
公开(公告)日：1999-10-05
申请号：US484170
申请日：1995-06-07
申请人： Adrian P. Wise , Kevin D. Dewar , Martin W. Sotheran
发明人： Adrian P. Wise , Kevin D. Dewar , Martin W. Sotheran
IPC分类号： H04N5/92 , G06F3/14 , G06F12/00 , G06F12/02 , G06F12/04 , G06F12/06 , G06F12/08 , G06F13/00 , G06F13/16 , G06F13/28 , G06F13/37 , G06T9/00 , G11B7/00 , G11B27/10 , H03M7/30 , H03M7/40 , H03M7/42 , H04L7/00 , H04L7/08 , H04L12/433 , H04N7/26 , H04N7/32 , H04N7/50 , H04N7/52
CPC分类号： H04N21/4307 , G06F12/0207 , G06F13/16 , G06F13/28 , H04N19/42 , H04N19/423 , H04N19/61 , H04N21/4305 , H04N21/44004 , G06F12/04 , H04N19/13 , H04N19/91
摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.
摘要翻译：一种MPEG视频解压缩方法和装置，利用被布置为流水线处理机的两线接口互连的多个级。控制令牌和数据令牌通过单个双线接口，以承载格式携带控制和数据。令牌解码电路位于某些阶段，用于将某些令牌识别为与该级相关的控制令牌，并沿着管道传递未被识别的控制令牌。重新配置处理电路定位在选定的阶段，并且响应于识别的控制令牌，以重新配置这样的阶段来处理所识别的数据令牌。公开了各种独特的支持子系统电路和处理技术，用于实现系统，包括存储器寻址，使用公共处理块变换数据，时间同步，异步摆动缓冲，存储视频信息，并行霍夫曼解码器等。

6. 发明授权

US5798719A Parallel Huffman decoder 失效
标题翻译：并行霍夫曼解码器
公开(公告)号：US5798719A
公开(公告)日：1998-08-25
申请号：US476814
申请日：1995-06-07
申请人： Adrian P. Wise , Kevin D. Dewar , Martin William Sotheran
发明人： Adrian P. Wise , Kevin D. Dewar , Martin William Sotheran
IPC分类号： H04N5/92 , G06F3/14 , G06F12/00 , G06F12/02 , G06F12/04 , G06F12/06 , G06F12/08 , G06F13/00 , G06F13/16 , G06F13/28 , G06F13/37 , G06T9/00 , G11B7/00 , G11B27/10 , H03M7/30 , H03M7/40 , H03M7/42 , H04L7/00 , H04L7/08 , H04L12/433 , H04N7/26 , H04N7/32 , H04N7/50 , H04N7/52
CPC分类号： H04N21/4307 , G06F12/0207 , G06F13/16 , G06F13/28 , H04N19/42 , H04N19/423 , H04N19/61 , H04N21/4305 , H04N21/44004 , G06F12/04 , H04N19/13 , H04N19/91
摘要： A Huffman Decoder is provided for decoding a data stream of fixed length and variable length codes and is adapted for video decompression applications. In the case of variable length codes, a table index calculation is performed using a ROM whose addresses are controlled by a selector/shifter. This calculation is bypassed in the case of fixed length codes. An index-to-data circuit then yields decoded data.
摘要翻译：提供霍夫曼解码器用于解码固定长度和可变长度码的数据流，并适用于视频解压缩应用。在可变长度码的情况下，使用由地址由选择器/移位器控制的ROM执行表索引计算。在固定长度代码的情况下，该计算被绕过。索引到数据电路然后产生解码的数据。

7. 发明授权

US5821885A Video decompression 失效
公开(公告)号：US5821885A
公开(公告)日：1998-10-13
申请号：US473813
申请日：1995-06-07
申请人： Adrian P. Wise , Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , Mark Barnes , Andrew Peter Kuligowski , William P. Robbins , Nicholas Birch , David Andrew Barnes
发明人： Adrian P. Wise , Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , Mark Barnes , Andrew Peter Kuligowski , William P. Robbins , Nicholas Birch , David Andrew Barnes
IPC分类号： H04N5/92 , G06F3/14 , G06F12/00 , G06F12/02 , G06F12/04 , G06F12/06 , G06F12/08 , G06F13/00 , G06F13/16 , G06F13/28 , G06F13/37 , G06T9/00 , G11B7/00 , G11B27/10 , H03M7/30 , H03M7/40 , H03M7/42 , H04L7/00 , H04L7/08 , H04L12/433 , H04N7/26 , H04N7/32 , H04N7/50 , H04N7/52
CPC分类号： H04N21/4307 , G06F12/0207 , G06F13/16 , G06F13/28 , H04N19/42 , H04N19/423 , H04N19/61 , H04N21/4305 , H04N21/44004 , G06F12/04 , H04N19/13 , H04N19/91
摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

8. 发明授权

US5740460A Arrangement for processing packetized data 失效
标题翻译：处理打包数据的安排
公开(公告)号：US5740460A
公开(公告)日：1998-04-14
申请号：US481772
申请日：1995-06-07
申请人： Adrian P. Wise , Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , Mark Barnes , Andrew Peter Kuligowski , William P. Robbins , Nicholas Birch , David Andrew Barnes
发明人： Adrian P. Wise , Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , Mark Barnes , Andrew Peter Kuligowski , William P. Robbins , Nicholas Birch , David Andrew Barnes
IPC分类号： H04N5/92 , G06F3/14 , G06F12/00 , G06F12/02 , G06F12/04 , G06F12/06 , G06F12/08 , G06F13/00 , G06F13/16 , G06F13/28 , G06F13/37 , G06T9/00 , G11B7/00 , G11B27/10 , H03M7/30 , H03M7/40 , H03M7/42 , H04L7/00 , H04L7/08 , H04L12/433 , H04N7/26 , H04N7/32 , H04N7/50 , H04N7/52 , G06F15/66
CPC分类号： H04N21/4307 , G06F12/0207 , G06F13/16 , G06F13/28 , H04N19/42 , H04N19/423 , H04N19/61 , H04N21/4305 , H04N21/44004 , G06F12/04 , H04N19/13 , H04N19/91
摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.
摘要翻译：一种MPEG视频解压缩方法和装置，利用被布置为流水线处理机的两线接口互连的多个级。控制令牌和数据令牌通过单个双线接口，以承载格式携带控制和数据。令牌解码电路位于某些阶段，用于将某些令牌识别为与该级相关的控制令牌，并沿着管道传递未被识别的控制令牌。重新配置处理电路定位在选定的阶段，并且响应于识别的控制令牌，以重新配置这样的阶段来处理所识别的数据令牌。公开了各种独特的支持子系统电路和处理技术，用于实现系统，包括存储器寻址，使用公共处理块变换数据，时间同步，异步摆动缓冲，存储视频信息，并行霍夫曼解码器等。

9. 发明授权

US5768629A Token-based adaptive video processing arrangement 失效
标题翻译：基于令牌的自适应视频处理布置
公开(公告)号：US5768629A
公开(公告)日：1998-06-16
申请号：US479910
申请日：1995-06-07
申请人： Adrian P. Wise , Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , Mark Barnes , Andrew Peter Kuligowski , William P. Robbins , Nicholas Birch , David Andrew Barnes
发明人： Adrian P. Wise , Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , Mark Barnes , Andrew Peter Kuligowski , William P. Robbins , Nicholas Birch , David Andrew Barnes
IPC分类号： H04N5/92 , G06F3/14 , G06F12/00 , G06F12/02 , G06F12/04 , G06F12/06 , G06F12/08 , G06F13/00 , G06F13/16 , G06F13/28 , G06F13/37 , G06T9/00 , G11B7/00 , G11B27/10 , H03M7/30 , H03M7/40 , H03M7/42 , H04L7/00 , H04L7/08 , H04L12/433 , H04N7/26 , H04N7/32 , H04N7/50 , H04N7/52
CPC分类号： H04N21/4307 , G06F12/0207 , G06F13/16 , G06F13/28 , H04N19/42 , H04N19/423 , H04N19/61 , H04N21/4305 , H04N21/44004 , G06F12/04 , H04N19/13 , H04N19/91
摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.
摘要翻译：一种MPEG视频解压缩方法和装置，利用被布置为流水线处理机的两线接口互连的多个级。控制令牌和数据令牌通过单个双线接口，以承载格式携带控制和数据。令牌解码电路位于某些阶段，用于将某些令牌识别为与该级相关的控制令牌，并沿着管道传递未被识别的控制令牌。重新配置处理电路定位在选定的阶段，并且响应于识别的控制令牌，以重新配置这样的阶段来处理所识别的数据令牌。公开了各种独特的支持子系统电路和处理技术，用于实现系统，包括存储器寻址，使用公共处理块变换数据，时间同步，异步摆动缓冲，存储视频信息，并行霍夫曼解码器等。

10. 发明授权

US06217234B1 Apparatus and method for processing data with an arithmetic unit 失效
标题翻译：用算术单元处理数据的装置和方法
公开(公告)号：US06217234B1
公开(公告)日：2001-04-17
申请号：US08487356
申请日：1995-06-07
申请人： Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , David Andrew Barnes
发明人： Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , David Andrew Barnes
IPC分类号： G06F1700
CPC分类号： H04N21/4307 , G06F12/0207 , G06F12/04 , G06F13/16 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91 , H04N21/4305 , H04N21/44004
摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.
摘要翻译：一种MPEG视频解压缩方法和装置，利用被布置为流水线处理机的两线接口互连的多个级。控制令牌和数据令牌通过单个双线接口，以承载格式携带控制和数据。令牌解码电路位于某些阶段，用于将某些令牌识别为与该级相关的控制令牌，并沿着管道传递未被识别的控制令牌。重新配置处理电路定位在选定的阶段，并且响应于识别的控制令牌，以重新配置这样的阶段来处理所识别的数据令牌。公开了各种独特的支持子系统电路和处理技术，用于实现系统，包括存储器寻址，使用公共处理块变换数据，时间同步，异步摆动缓冲，存储视频信息，并行霍夫曼解码器等。

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