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1. 发明授权

US5166552A Multi-emitter BICMOS logic circuit family with superior performance 失效
标题翻译：具有超级性能的多发发射体BICMOS逻辑电路系列
公开(公告)号：US5166552A
公开(公告)日：1992-11-24
申请号：US659404
申请日：1991-03-08
申请人： Anthony G. Aipperspach , Gerard Boudon , Allan H. Dansky , Pierre Mollier , Ieng Ong , Nghia Phan , Biagio Pluchino , Steven J. Zier , Adrian Zuckerman
发明人： Anthony G. Aipperspach , Gerard Boudon , Allan H. Dansky , Pierre Mollier , Ieng Ong , Nghia Phan , Biagio Pluchino , Steven J. Zier , Adrian Zuckerman
IPC分类号： H03K19/08 , H03K19/013 , H03K19/017 , H03K19/0944 , H03K19/21
CPC分类号： H03K19/013 , H03K19/01707 , H03K19/09448 , H03K19/215
摘要： A multi emitter multi input BICMOS NAND circuit (30) is provided wherein an output node OUT connected to an output terminal (33) is coupled between pull up (31) and pull down (32) blocks. According to one embodiment of the present invention, the pull up block (32) is comprised of a plurality of identical basic cells, each comprised of a CMOS inverter (C31, C32) driving an NPN pull up transistor (T31, T32) mounted as an emitter follower. Logic signals (A31, A32) are applied on the inputs of the inverters (C31, C32), and the inverted signal (A31, A32) is available at the emitter of the emitter follower which corresponds to the output of the cell. All outputs are tied altogether to perform an OR function and are connected to said output terminal (33) to have a multi emitter like circuit. The pull down block (32) in this embodiment is comprised of 2 FETs (F31, F32) serially connected between said output node OUT and a discharge device such as a feedback NFET (Z) the gate of which is connected to said output node OUT. These 2 FETs are for driving a NPN pull down transistor (T), the collector of which is also connected to the output node OUT. The invention includes a number of other embodiments including a feedback inverter embodiment, a parasitic node discharge embodiment, and a BIFET latch embodiment.

2. 发明授权

US4746817A BIFET logic circuit 失效
标题翻译： BIFET逻辑电路
公开(公告)号：US4746817A
公开(公告)日：1988-05-24
申请号：US26229
申请日：1987-03-16
申请人： Dennis C. Banker , Allan H. Dansky , Jack A. Dorler , Walter S. Klara , Frank M. Masci , Steven J. Zier , Adrian Zuckerman
发明人： Dennis C. Banker , Allan H. Dansky , Jack A. Dorler , Walter S. Klara , Frank M. Masci , Steven J. Zier , Adrian Zuckerman
IPC分类号： H03K19/01 , H03K17/04 , H03K17/567 , H03K19/00 , H03K19/08 , H03K19/0944
CPC分类号： H03K19/001 , H03K19/09448
摘要： A BIFET logic circuit for quickly switching an output line from a high level to a reference level. The BICMOS circuit comprises a push-pull circuit including a first bipolar transistor for driving current into an output line, and a second bipolar transistor for sinking current from the output line; a CFET logic circuit for performing a logic function and including at least one N type FET for providing current to the base of the second bipolar transistor when a set of input lines to the CFET circuit has a first set of predetermined values; and a resistive means for connecting one of the source or drain of the at least one NFET to a power supply to provide a source of base current to the second bipolar transistor, even when the output line drops in voltage. This circuit is especially advantageous for driving low threshold CFET circuits. In a preferred embodiment, the circuit further includes a device for preventing a voltage differential of more than a predetermined amount between the base and emitter of the first bipolar transistor, to thereby ensure proper push-pull operation of the bipolar transistors.

3. 发明授权

US6028989A Calculating crosstalk voltage from IC craftsman routing data 失效
标题翻译：从IC工匠路由数据计算串扰电压
公开(公告)号：US6028989A
公开(公告)日：2000-02-22
申请号：US059220
申请日：1998-04-13
申请人： Allan Harvey Dansky , Howard Harold Smith , Fadi Yusuf Busaba , Michael Alexander Bowen , Adrian Zuckerman
发明人： Allan Harvey Dansky , Howard Harold Smith , Fadi Yusuf Busaba , Michael Alexander Bowen , Adrian Zuckerman
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5036
摘要： A program method for noise calculation and modeling caculates crosstalk voltage for a planned chip design, by first running routing and crosstalk routines for creating crosstalk rules for the planned design of a chip and loading crosstalk rules after routing is completed, and calculating the noise voltage of the planned design based on the exact topologies/paths of the victim and perpetrator nets of the planned design by path tracing and outputing a program file which contains the calculated noise voltage and a complete tabulation of the key physical and electrical parameters of the victim and perpetrator nets of the planned design, and then modeling using a network analysis program to selected nets of the design which exceed allowed noise limitations and obtaining the planned design net's network topology as an output while using the program file containing noise voltage calculation results as an input to the net's topology circuit simulation modeling program and outputting a nodal voltages vs. time data at each receiver location on a victim net as well as key nodes on any perpetrator nets of said planned design.
摘要翻译：用于噪声计算和建模的程序方法通过首先运行路由和串扰例程来产生计划的芯片设计的串扰电压，以便在路由完成之后为芯片的计划设计设计串扰规则并加载串扰规则，并计算噪声电压基于确定的受害者的拓扑/路径和计划设计的犯罪网络的计划设计，通过路径跟踪并输出包含计算的噪声电压的程序文件，以及完整列出受害者和肇事者的主要物理和电气参数网络的计划设计，然后使用网络分析程序对设计的选定网络进行建模，超过允许的噪声限制，并将计划设计网络的网络拓扑结构作为输出，同时使用包含噪声电压计算结果的程序文件作为输入网络拓扑电路仿真建模程序并输出节点在受害者网络上的每个接收者位置处的时间数据与时间数据以及所述计划设计的任何犯罪网络上的关键节点。

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