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1. 发明授权

US07705385B2 Selective deposition of germanium spacers on nitride 失效
标题翻译：锗间隔物选择性沉积在氮化物上
公开(公告)号：US07705385B2
公开(公告)日：2010-04-27
申请号：US10905587
申请日：2005-09-12
申请人： Ashima Chakravarti , Anthony Chou , Toshiharu Furukawa , Steven Holmes , Wesley Natzle
发明人： Ashima Chakravarti , Anthony Chou , Toshiharu Furukawa , Steven Holmes , Wesley Natzle
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119 , H01L29/00
CPC分类号： H01L29/7833 , H01L21/02532 , H01L21/02587 , H01L21/0262 , H01L21/02639 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L2224/05571 , H01L2224/05573 , H01L2224/10126 , H01L2224/13023 , H01L2924/1305 , H01L2924/00
摘要： A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.
摘要翻译：在半导体制造工艺中选择性地形成锗结构的方法在化学氧化物去除（COR）工艺中从氮化物表面去除天然氧化物，然后将加热的氮化物和氧化物表面暴露于加热的含锗气体，以仅选择性地形成锗氮化物表面而不是氧化物表面。

2. 发明申请

US20060057811A1 Selective post-doping of gate structures by means of selective oxide growth 失效
标题翻译：通过选择性氧化物生长选择性地掺杂栅极结构
公开(公告)号：US20060057811A1
公开(公告)日：2006-03-16
申请号：US11268100
申请日：2005-11-07
申请人： Anthony Chou , Toshiharu Furukawa , Steven Holmes
发明人： Anthony Chou , Toshiharu Furukawa , Steven Holmes
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/6659 , H01L21/02131 , H01L21/02164 , H01L21/02282 , H01L21/02304 , H01L21/266 , H01L21/316 , H01L21/31612 , H01L21/823814 , H01L21/823842 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： A method for doping a polysilicon gate conductor, without implanting the substrate in a manner that would effect source/drain formation is provided. The inventive method comprises forming at least one polysilicon gate region atop a substrate; forming oxide seed spacers abutting the polysilicon gate; forming source/drain oxide spacers selectively deposited on the oxide seed spacers by liquid phase deposition, and implanting at least one polysilicon gate region, wherein the source/drain oxide spacers protect an underlying portion of the substrate. Multiple gate regions may be processed on a single substrate using conventional patterning. A block-mask provided by patterned photoresist can be used prior to implantation to pre-select the substrate area for gate conductor doping with one dopant type.
摘要翻译：提供了掺杂多晶硅栅极导体而不以将影响源极/漏极形成的方式植入衬底的方法。本发明的方法包括在基板顶上形成至少一个多晶硅栅极区域; 形成邻接所述多晶硅栅极的氧化物种子间隔物; 通过液相沉积选择性地沉积在氧化物种间隔物上的源极/漏极氧化物间隔区，以及注入至少一个多晶硅栅极区域，其中源极/漏极氧化物间隔物保护衬底的下面部分。可以使用常规图案化在单个基板上处理多个栅极区域。在植入之前可以使用由图案化的光致抗蚀剂提供的块掩模，以预先选择用于掺杂一种掺杂剂类型的栅极导体的衬底区域。

3. 发明申请

US20070059894A1 SELECTIVE DEPOSITION OF GERMANIUM SPACERS ON NITRIDE 失效
标题翻译：硝酸盐选择性沉积氮离子
公开(公告)号：US20070059894A1
公开(公告)日：2007-03-15
申请号：US10905587
申请日：2005-09-12
申请人： Ashima Chakravarti , Anthony Chou , Toshiharu Furukawa , Steven Holmes , Wesley Natzle
发明人： Ashima Chakravarti , Anthony Chou , Toshiharu Furukawa , Steven Holmes , Wesley Natzle
IPC分类号： H01L21/336 , H01L21/44 , H01L21/20
CPC分类号： H01L29/7833 , H01L21/02532 , H01L21/02587 , H01L21/0262 , H01L21/02639 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L2224/05571 , H01L2224/05573 , H01L2224/10126 , H01L2224/13023 , H01L2924/1305 , H01L2924/00
摘要： A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.
摘要翻译：在半导体制造工艺中选择性地形成锗结构的方法在化学氧化物去除（COR）工艺中从氮化物表面去除天然氧化物，然后将加热的氮化物和氧化物表面暴露于加热的含锗气体，以仅选择性地形成锗氮化物表面而不是氧化物表面。

4. 发明申请

US20050148144A1 Selective post-doping of gate structures by means of selective oxide growth 失效
标题翻译：通过选择性氧化物生长选择性地掺杂栅极结构
公开(公告)号：US20050148144A1
公开(公告)日：2005-07-07
申请号：US10732657
申请日：2003-12-10
申请人： Anthony Chou , Toshiharu Furukawa , Steven Holmes
发明人： Anthony Chou , Toshiharu Furukawa , Steven Holmes
IPC分类号： H01L21/266 , H01L21/316 , H01L21/336 , H01L21/8238 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/02131 , H01L21/02164 , H01L21/02282 , H01L21/02304 , H01L21/266 , H01L21/316 , H01L21/31612 , H01L21/823814 , H01L21/823842 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： A method for doping a polysilicon gate conductor, without implanting the substrate in a manner that would effect source/drain formation is provided. The inventive method comprises forming at least one polysilicon gate region atop a substrate; forming oxide seed spacers abutting the polysilicon gate; forming source/drain oxide spacers selectively deposited on the oxide seed spacers by liquid phase deposition, and implanting at least one polysilicon gate region, wherein the source/drain oxide spacers protect an underlying portion of the substrate. Multiple gate regions may be processed on a single substrate using conventional patterning. A block-mask provided by patterned photoresist can be used prior to implantation to pre-select the substrate area for gate conductor doping with one dopant type.
摘要翻译：提供了掺杂多晶硅栅极导体而不以将影响源极/漏极形成的方式植入衬底的方法。本发明的方法包括在基板顶上形成至少一个多晶硅栅极区域; 形成邻接所述多晶硅栅极的氧化物种子间隔物; 通过液相沉积选择性地沉积在氧化物种间隔物上的源极/漏极氧化物间隔区，以及注入至少一个多晶硅栅极区域，其中源极/漏极氧化物间隔物保护衬底的下面部分。可以使用常规图案化在单个基板上处理多个栅极区域。在植入之前可以使用由图案化的光致抗蚀剂提供的块掩模，以预先选择用于掺杂一种掺杂剂类型的栅极导体的衬底区域。

5. 发明申请

US20080090379A1 Nitridation of STI Fill Oxide to Prevent the Loss of STI Fill Oxide During Manufacturing Process 失效
标题翻译：氮化硅填充氧化物，以防止在制造过程中STI填充氧化物的损失
公开(公告)号：US20080090379A1
公开(公告)日：2008-04-17
申请号：US11955751
申请日：2007-12-13
申请人： Fred Buehrer , Anthony Chou , Toshiharu Furukawa , Renee Mo
发明人： Fred Buehrer , Anthony Chou , Toshiharu Furukawa , Renee Mo
IPC分类号： H01L21/76
CPC分类号： H01L21/76232 , H01L21/76224 , H01L21/823481
摘要： A method and structure for an improved shallow trench isolation (STI) structure for a semiconductor device. The STI structure incorporates an oxynitride top layer of the STI fill. Optionally, the STI structure incorporates an oxynitride margin of the STI fill adjacent the silicon trench walls. A region of the oxynitride margin near the upper edges of the silicon trench walls includes oxynitride corners that are relatively thicker and contain a higher concentration of nitrogen as compared to the other regions of the oxynitride margin. The oxynitride features limit the STI fill height loss and also reduce the formation of divots in the STI fill below the level of the silicon substrate cause by hydrofluoric acid etching and other fabrication processes. Limiting STI fill height loss and the formation of divots improves the functions of the STI structure. The method of forming the STI structure is particularly compatible with standard semiconductor device fabrication processes, including chemical mechanical polishing (CMP), because the method incorporates the use of a pure silicon dioxide STI fill and plasma and thermal nitridation processes to form the oxynitride top layer and oxynitride margin, including the oxynitride corners, of the STI fill.
摘要翻译：一种用于半导体器件的改进的浅沟槽隔离（STI）结构的方法和结构。 STI结构包含STI填充物的氮氧化物顶层。可选地，STI结构包括邻近硅沟槽壁的STI填充的氮氧化物边缘。在硅沟槽壁的上边缘附近的氮氧化物边缘的区域包括与氮氧化物边缘的其它区域相比相对较厚并且含有较高浓度的氮的氧氮化物角。氮氧化物的特征是限制了STI填充高度损失，并且还减少了STI填充物中由于氢氟酸蚀刻和其它制造工艺引起的硅衬底的形成。限制STI填充高度损失和形成纹理改善了STI结构的功能。形成STI结构的方法与包括化学机械抛光（CMP）在内的标准半导体器件制造工艺特别兼容，因为该方法包括使用纯二氧化硅STI填充和等离子体和热氮化工艺来形成氧氮化物顶层和氮氧化物边缘，包括氮氧化物拐角，STI填充。

6. 发明申请

US20060160322A1 NITRIDATION OF STI FILL OXIDE TO PREVENT THE LOSS OF STI FILL OXIDE DURING MANUFACTURING PROCESS 失效
标题翻译：氮化硅氧化物在制造过程中防止氧化硅损失
公开(公告)号：US20060160322A1
公开(公告)日：2006-07-20
申请号：US10905683
申请日：2005-01-17
申请人： Fred Buehrer , Anthony Chou , Toshiharu Furukawa , Renee Mo
发明人： Fred Buehrer , Anthony Chou , Toshiharu Furukawa , Renee Mo
IPC分类号： H01L21/76
CPC分类号： H01L21/76232 , H01L21/76224 , H01L21/823481
摘要： A method and structure for an improved shallow trench isolation (STI) structure for a semiconductor device. The STI structure incorporates an oxynitride top layer of the STI fill. Optionally, the STI structure incorporates an oxynitride margin of the STI fill adjacent the silicon trench walls. A region of the oxynitride margin near the upper edges of the silicon trench walls includes oxynitride corners that are relatively thicker and contain a higher concentration of nitrogen as compared to the other regions of the oxynitride margin. The oxynitride features limit the STI fill height loss and also reduce the formation of divots in the STI fill below the level of the silicon substrate cause by hydrofluoric acid etching and other fabrication processes. Limiting STI fill height loss and the formation of divots improves the functions of the STI structure. The method of forming the STI structure is particularly compatible with standard semiconductor device fabrication processes, including chemical mechanical polishing (CMP), because the method incorporates the use of a pure silicon dioxide STI fill and plasma and thermal nitridation processes to form the oxynitride top layer and oxynitride margin, including the oxynitride corners, of the STI fill.
摘要翻译：一种用于半导体器件的改进的浅沟槽隔离（STI）结构的方法和结构。 STI结构包含STI填充物的氮氧化物顶层。可选地，STI结构包括邻近硅沟槽壁的STI填充的氮氧化物边缘。在硅沟槽壁的上边缘附近的氮氧化物边缘的区域包括与氮氧化物边缘的其它区域相比相对较厚并且含有较高浓度的氮的氧氮化物角。氮氧化物的特征是限制了STI填充高度损失，并且还减少了STI填充物中由于氢氟酸蚀刻和其它制造工艺引起的硅衬底的形成。限制STI填充高度损失和形成纹理改善了STI结构的功能。形成STI结构的方法与包括化学机械抛光（CMP）在内的标准半导体器件制造工艺特别兼容，因为该方法包括使用纯二氧化硅STI填充和等离子体和热氮化工艺来形成氧氮化物顶层和氮氧化物边缘，包括氮氧化物拐角，STI填充。

7. 发明申请

US20050118764A1 Forming gate oxides having multiple thicknesses 失效
标题翻译：形成具有多个厚度的栅极氧化物
公开(公告)号：US20050118764A1
公开(公告)日：2005-06-02
申请号：US10724483
申请日：2003-11-28
申请人： Anthony Chou , Michael Chudzik , Toshiharu Furukawa , Oleg Gluschenkov , Paul Kirsch , Byoung Lee , Katsunori Onishi , Heemyoung Park , Kristen Scheer , Akihisa Sekiguchi
发明人： Anthony Chou , Michael Chudzik , Toshiharu Furukawa , Oleg Gluschenkov , Paul Kirsch , Byoung Lee , Katsunori Onishi , Heemyoung Park , Kristen Scheer , Akihisa Sekiguchi
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/00 , H01L21/3205 , H01L21/336 , H01L21/84
CPC分类号： H01L21/823462 , H01L21/823857
摘要： Gate oxides having different thicknesses are formed on a semiconductor substrate by forming a first gate oxide on the top surface of the substrate, forming a sacrificial hard mask over a selected area of the first gate oxide; and then forming a second gate oxide. A first poly layer may be formed on the first gate oxide, under the hard mask. After the hard mask is removed, a second poly layer may be formed over the second gate oxide and over the first poly layer. This enables the use of high-k dielectric materials, and the first gate oxide can be thinner than the second gate oxide.
摘要翻译：通过在衬底的顶表面上形成第一栅极氧化物，在半导体衬底上形成具有不同厚度的栅极氧化物，在第一栅极氧化物的选定区域上形成牺牲性硬掩模; 然后形成第二栅极氧化物。可以在硬掩模下的第一栅极氧化物上形成第一多晶硅层。在去除硬掩模之后，可以在第二栅极氧化物之上和第一多晶硅层上形成第二多晶硅层。这使得能够使用高k电介质材料，并且第一栅极氧化物可以比第二栅极氧化物薄。

8. 发明申请

US20120123894A1 Decentralized Transportation Dispatching System and Method for Decentralized Transportation Dispatching 审中-公开
标题翻译：分散式运输调度系统及分散式运输调度方法
公开(公告)号：US20120123894A1
公开(公告)日：2012-05-17
申请号：US13295198
申请日：2011-11-14
申请人： Frank Chee-Da Tsai , Anthony Chou , Wen-Yao Chang
发明人： Frank Chee-Da Tsai , Anthony Chou , Wen-Yao Chang
IPC分类号： G06Q50/30 , G06Q30/06
CPC分类号： G06Q30/0611
摘要： A method for decentralized transportation dispatching is disclosed. The method bypasses utilizing a centralized dispatch call center and includes announcing a transportation requirement via broadcasting directly by at least one user, and replying to the transportation requirement with a plurality of competitive bidding information directly from a plurality of transportation providers who are capable of providing a passenger-carrying service or providing a goods-carrying service. The method further includes selecting one transportation provider from the transportation providers according to a request from the user, in which the selecting is performed through referencing the bidding information replied to by the transportation providers.
摘要翻译：披露了分散运输调度方法。该方法绕过利用集中式调度呼叫中心，并且包括通过至少一个用户直接广播来宣布交通需求，并且直接从能够提供一个用户的多个运输提供商的多个竞争性投标信息中回答运输需求乘客携带服务或提供货物服务。该方法还包括根据来自用户的请求从运输提供商中选择一个运输提供商，其中通过参考由运输提供商回复的投标信息进行选择。

9. 发明授权

US07235440B2 Formation of ultra-thin oxide layers by self-limiting interfacial oxidation 有权
标题翻译：通过自限界面氧化形成超薄氧化层
公开(公告)号：US07235440B2
公开(公告)日：2007-06-26
申请号：US10630969
申请日：2003-07-31
申请人： David L O'Meara , Cory Wajda , Anthony Dip , Michael Toeller , Toshihara Furukawa , Kristen Scheer , Alessandro Callegari , Fred Buehrer , Sufi Zafar , Evgeni Gousev , Anthony Chou , Paul Higgins
发明人： David L O'Meara , Cory Wajda , Anthony Dip , Michael Toeller , Toshihara Furukawa , Kristen Scheer , Alessandro Callegari , Fred Buehrer , Sufi Zafar , Evgeni Gousev , Anthony Chou , Paul Higgins
IPC分类号： H01L21/8242
CPC分类号： H01L21/28194 , H01L21/02238 , H01L21/02255 , H01L21/28167 , H01L21/28202 , H01L21/28211 , H01L21/3144 , H01L21/31604 , H01L21/31616 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31662 , H01L29/513 , H01L29/517 , H01L29/518
摘要： Ultra-thin oxide layers are formed utilizing low pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxide. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, a nitride layer, a high-k layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or, alternatively, using a single-wafer process chamber. One embodiment of the invention provides self-limiting oxidation of Si-substrates that results in SiO2 layers with a thickness of about 15 A, where the thickness of the SiO2 layers varies less than about 1 A over the substrates.
摘要翻译：使用低压处理形成超薄氧化层，以实现衬底的自限制氧化并提供超薄氧化物。待处理的基板可以包含初始介电层，例如氧化物层，氧氮化物层，氮化物层，高k层，或者可以缺少初始介电层。处理可以使用间歇式处理室进行，或者使用单晶圆处理室进行。本发明的一个实施例提供了Si衬底的自限制氧化，其导致厚度为约15A的SiO 2层，其中SiO 2层的厚度在基材上变化小于约1A。

10. 发明申请

US20070010050A1 METHOD FOR FORMING SEMICONDUCTOR DEVICES HAVING REDUCED GATE EDGE LEAKAGE CURRENT 有权
标题翻译：用于形成具有降低的栅极边缘漏电流的半导体器件的方法
公开(公告)号：US20070010050A1
公开(公告)日：2007-01-11
申请号：US11160700
申请日：2005-07-06
申请人： Anthony Chou , Shreesh Narasimha
发明人： Anthony Chou , Shreesh Narasimha
IPC分类号： H01L21/8234
CPC分类号： H01L21/28176 , H01L29/512 , H01L29/517 , H01L29/518 , H01L29/7833
摘要： The present invention provides methods for forming semiconductor FET devices having reduced gate edge leakage current by using plasma or thermal nitridation and low-temperature plasma re-oxidation processes post gate etch.
摘要翻译：本发明提供了通过使用栅极蚀刻后的等离子体或热氮化和低温等离子体再氧化工艺形成具有减小的栅极边缘漏电流的半导体FET器件的方法。

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