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1. 发明授权

US07843264B2 Differential amplifier with accurate input offset voltage 有权
标题翻译：具有精确输入失调电压的差分放大器
公开(公告)号：US07843264B2
公开(公告)日：2010-11-30
申请号：US12021477
申请日：2008-01-29
申请人： Anosh B. Davierwalla , Chul Kyu Lee , Vannam Dang
发明人： Anosh B. Davierwalla , Chul Kyu Lee , Vannam Dang
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/45192 , H03F3/45766 , H03F2200/453 , H03F2200/456 , H03F2203/45028 , H03F2203/45048 , H03F2203/45286 , H03F2203/45291 , H03F2203/45294 , H03F2203/45624 , H03F2203/45628 , H03K5/2481
摘要： An amplifier with accurate input offset voltage is described. In one design, the amplifier includes first and second unbalanced differential pairs. The first unbalanced differential pair receives a differential input signal and provides a first differential current signal. The second unbalanced differential pair receives a differential reference signal and provides a second differential current signal, which is subtracted from the first differential current signal to obtain a differential output signal. The second differential current signal tracks an error current in the first differential current signal so that the differential output signal is zero when the differential input signal is equal to a target input offset voltage for the amplifier. For each unbalanced differential pair, one transistor is M times the size of the other transistor, with M being selected to obtain the target input offset voltage.
摘要翻译：描述了具有精确输入失调电压的放大器。在一种设计中，放大器包括第一和第二不平衡差分对。第一不平衡差分对接收差分输入信号并提供第一差分电流信号。第二不平衡差分对接收差分参考信号，并提供从第一差分电流信号中减去的第二差分电流信号，以获得差分输出信号。第二差分电流信号跟踪第一差分电流信号中的误差电流，使得当差分输入信号等于放大器的目标输入失调电压时，差分输出信号为零。对于每个不平衡差分对，一个晶体管是另一个晶体管尺寸的M倍，其中M被选择以获得目标输入偏移电压。

2. 发明申请

US20090189694A1 DIFFERENTIAL AMPLIFIER WITH ACCURATE INPUT OFFSET VOLTAGE 有权
标题翻译：具有精确输入偏置电压的差分放大器
公开(公告)号：US20090189694A1
公开(公告)日：2009-07-30
申请号：US12021477
申请日：2008-01-29
申请人： Anosh B. Davierwalla , Chul Kyu Lee , Vannam Dang
发明人： Anosh B. Davierwalla , Chul Kyu Lee , Vannam Dang
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/45192 , H03F3/45766 , H03F2200/453 , H03F2200/456 , H03F2203/45028 , H03F2203/45048 , H03F2203/45286 , H03F2203/45291 , H03F2203/45294 , H03F2203/45624 , H03F2203/45628 , H03K5/2481
摘要： An amplifier with accurate input offset voltage is described. In one design, the amplifier includes first and second unbalanced differential pairs. The first unbalanced differential pair receives a differential input signal and provides a first differential current signal. The second unbalanced differential pair receives a differential reference signal and provides a second differential current signal, which is subtracted from the first differential current signal to obtain a differential output signal. The second differential current signal tracks an error current in the first differential current signal so that the differential output signal is zero when the differential input signal is equal to a target input offset voltage for the amplifier. For each unbalanced differential pair, one transistor is M times the size of the other transistor, with M being selected to obtain the target input offset voltage.
摘要翻译：描述了具有精确输入失调电压的放大器。在一种设计中，放大器包括第一和第二不平衡差分对。第一不平衡差分对接收差分输入信号并提供第一差分电流信号。第二不平衡差分对接收差分参考信号，并提供从第一差分电流信号中减去的第二差分电流信号，以获得差分输出信号。第二差分电流信号跟踪第一差分电流信号中的误差电流，使得当差分输入信号等于放大器的目标输入偏移电压时，差分输出信号为零。对于每个不平衡差分对，一个晶体管是另一个晶体管尺寸的M倍，其中M被选择以获得目标输入偏移电压。

3. 发明授权

US08760189B2 Apparatus to implement symmetric single-ended termination in differential voltage-mode drivers 有权
标题翻译：在差分电压模式驱动器中实现对称单端端接的装置
公开(公告)号：US08760189B2
公开(公告)日：2014-06-24
申请号：US13248485
申请日：2011-09-29
申请人： Cheng Zhong , Vannam Dang , Miao Li , Fares K. Maarouf , Tirdad Sowlati
发明人： Cheng Zhong , Vannam Dang , Miao Li , Fares K. Maarouf , Tirdad Sowlati
IPC分类号： H03K17/16
CPC分类号： H04L25/0274 , H04L25/0278
摘要： A differential voltage mode driver for implementing symmetric single ended termination includes an output driver circuitry having a predefined termination impedance. The differential voltage mode driver also includes an output driver replica having independently controlled first and second portions. The first and second portions are independently controlled to establish a substantially equal on-resistance of the first and the second portions. The output driver replica controls the predefined termination impedance of the output driver circuitry.
摘要翻译：用于实现对称单端终端的差分电压模式驱动器包括具有预定义的终端阻抗的输出驱动器电路。差分电压模式驱动器还包括具有独立控制的第一和第二部分的输出驱动器副本。独立地控制第一和第二部分以建立第一和第二部分的基本相等的导通电阻。输出驱动器副本控制输出驱动器电路的预定终止阻抗。

4. 发明授权

US08390314B2 Method of half-bit pre-emphasis for multi-level signal 有权
标题翻译：半电平信号的半位预加重方法
公开(公告)号：US08390314B2
公开(公告)日：2013-03-05
申请号：US13006451
申请日：2011-01-14
申请人： Harry H. Dang , Vannam Dang
发明人： Harry H. Dang , Vannam Dang
IPC分类号： H03K19/003
CPC分类号： H04L25/03834
摘要： Methods and apparatus for improving transmission channel efficiency are provided. In an example, a digital signal is received. A leading portion of a bit in the digital signal is pre-emphasized. The received digital signal is modulated with a pre-emphasis signal to pre-emphasize a leading portion of the bit in the digital signal. The pre-emphasis signal provides pre-emphasis substantially when a clock is high and the received digital signal transitions. The pre-emphasis signal does not provide pre-emphasis when the received digital signal is low or the received digital signal is unchanged. The pre-emphasized digital signal is then transmitted via the transmission channel. In an example, the received digital signal us a pulse-amplitude modulated multilevel signal.
摘要翻译：提供了改善传输通道效率的方法和装置。在一个示例中，接收数字信号。预先强调数字信号中的位的前导部分。接收到的数字信号用预加重信号进行调制，以预先强调数字信号中位的前导部分。预加重信号基本上在时钟为高并且所接收的数字信号转变时提供预加重。当接收的数字信号为低或接收的数字信号不变时，预加重信号不提供预加重。然后通过传输信道传输预先强调的数字信号。在一个例子中，接收到的数字信号是脉冲幅度调制多电平信号。

5. 发明申请

US20130033329A1 System and Method of Controlling Gain of an Oscillator 失效
标题翻译：控制振荡器增益的系统和方法
公开(公告)号：US20130033329A1
公开(公告)日：2013-02-07
申请号：US13204267
申请日：2011-08-05
申请人： Zhi Zhu , Xiaohua Kong , Vannam Dang , Cheng Zhong
发明人： Zhi Zhu , Xiaohua Kong , Vannam Dang , Cheng Zhong
IPC分类号： H03L7/00
CPC分类号： H03L7/099 , H03L1/00 , H03L2207/06
摘要： A circuit includes a controllable oscillator and a controller coupled to the controllable oscillator. The controller is configured to provide a current control and a gain control to the controllable oscillator. The gain control is configured to change a gain of the controllable oscillator during a calibration process.
摘要翻译：电路包括可控振荡器和耦合到可控振荡器的控制器。控制器被配置为向可控振荡器提供电流控制和增益控制。增益控制被配置为在校准过程期间改变可控振荡器的增益。

6. 发明授权

US08634510B2 Full digital bang bang frequency detector with no data pattern dependency 失效
标题翻译：全数字爆炸频率检测器，无数据模式依赖
公开(公告)号：US08634510B2
公开(公告)日：2014-01-21
申请号：US13005271
申请日：2011-01-12
申请人： Xiaohua Kong , Vannam Dang , Tirdad Sowlati
发明人： Xiaohua Kong , Vannam Dang , Tirdad Sowlati
IPC分类号： H04L7/02
CPC分类号： H04L7/033 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/087 , H03L7/091 , H03L7/0995
摘要： A bang-bang frequency detector with no data pattern dependency is provided. In examples, the detector recovers a clock from received data, such as data having a non-return to zero (NRZ) format. A first bang-bang phase detector (BBPD) provides first phase information about a phase difference between a sample clock and the clock embedded in the received data. A second BBPD provides second phase information about a second phase difference between the clock embedded in the received data and a delayed version of the sample clock. A frequency difference between the sample clock and the clock embedded in the received data is determined based on the first and second phase differences. The frequency difference can be used to adjust the frequency of the sample clock. A lock detector can be coupled to a BBPD output to determine if the sample clock is locked to the clock embedded in the received data.
摘要翻译：提供了一种没有数据模式依赖性的爆轰频率检测器。在示例中，检测器从接收的数据恢复时钟，例如具有不归零（NRZ）格式的数据。第一个爆炸相位检测器（BBPD）提供关于采样时钟和嵌入在接收数据中的时钟之间的相位差的第一阶段信息。第二BBPD提供关于嵌入在接收数据中的时钟与采样时钟的延迟版本之间的第二相位差的第二阶段信息。基于第一和第二相位差来确定采样时钟和嵌入在接收数据中的时钟之间的频率差。频率差可用于调整采样时钟的频率。锁定检测器可以耦合到BBPD输出，以确定采样时钟是否锁定在嵌入在接收数据中的时钟。

7. 发明申请

US20080290924A1 METHOD AND APPARATUS FOR PROGRAMMABLE DELAY HAVING FINE DELAY RESOLUTION 审中-公开
标题翻译：具有精细延迟分辨率的可编程延迟的方法和装置
公开(公告)号：US20080290924A1
公开(公告)日：2008-11-27
申请号：US12116516
申请日：2008-05-07
申请人： Jason Gonzalez , Harry H. Dang , Vannam Dang
发明人： Jason Gonzalez , Harry H. Dang , Vannam Dang
IPC分类号： H03H11/26
CPC分类号： H03K5/131 , H03K2005/00058 , H03K2005/00234
摘要： An programmable delay apparatus includes a first delay stage having a delay cell which includes a passive network, where the first delay stage is capable of providing a first time delay. The apparatus further includes a second delay stage which includes a plurality of delay cells, where each delay cell is capable of providing a second time delay which is larger than the first time delay. A method for delaying an input signal includes receiving a delay select command based upon the desired time delay, establishing a circuit path which includes at least one delay element, selected from a plurality of delay cells, according to the delay select command, wherein at least one of the plurality of delay cells includes a delay element which comprises a passive network.
摘要翻译：可编程延迟装置包括具有包括无源网络的延迟单元的第一延迟级，其中第一延迟级能够提供第一时间延迟。该装置还包括第二延迟级，其包括多个延迟单元，其中每个延迟单元能够提供大于第一时间延迟的第二时间延迟。一种用于延迟输入信号的方法包括基于所需的时间延迟接收延迟选择命令，根据延迟选择命令建立包括从多个延迟单元中选择的至少一个延迟元件的电路，其中至少所述多个延迟单元中的一个包括包括无源网络的延迟元件。

8. 发明授权

US09143121B2 System and method of adjusting a clock signal 有权
标题翻译：调整时钟信号的系统和方法
公开(公告)号：US09143121B2
公开(公告)日：2015-09-22
申请号：US13598513
申请日：2012-08-29
申请人： Jason Gonzalez , Vannam Dang , Zhi Zhu
发明人： Jason Gonzalez , Vannam Dang , Zhi Zhu
IPC分类号： H03K3/017 , H03K7/08 , H03K5/156
CPC分类号： H03K5/1565
摘要： A method includes receiving an input clock signal at a programmable buffer. The method further includes filtering an output signal from the programmable buffer to generate a filtered signal having a voltage level, where the voltage level indicates a duty cycle of the output signal. The method further includes comparing the voltage level to a reference voltage. The method further includes modifying at least one operating parameter of the programmable buffer to adjust the duty cycle of the output signal.
摘要翻译：一种方法包括在可编程缓冲器处接收输入时钟信号。该方法还包括对来自可编程缓冲器的输出信号进行滤波以产生具有电压电平的滤波信号，其中电压电平指示输出信号的占空比。该方法还包括将电压电平与参考电压进行比较。该方法还包括修改可编程缓冲器的至少一个操作参数以调整输出信号的占空比。

9. 发明申请

US20140062559A1 SYSTEM AND METHOD OF ADJUSTING A CLOCK SIGNAL 有权
标题翻译：调整时钟信号的系统和方法
公开(公告)号：US20140062559A1
公开(公告)日：2014-03-06
申请号：US13598513
申请日：2012-08-29
申请人： Jason Gonzalez , Vannam Dang , Zhi Zhu
发明人： Jason Gonzalez , Vannam Dang , Zhi Zhu
IPC分类号： H03K5/156
CPC分类号： H03K5/1565
摘要： A method includes receiving an input clock signal at a programmable buffer. The method further includes filtering an output signal from the programmable buffer to generate a filtered signal having a voltage level, where the voltage level indicates a duty cycle of the output signal. The method further includes comparing the voltage level to a reference voltage. The method further includes modifying at least one operating parameter of the programmable buffer to adjust the duty cycle of the output signal.
摘要翻译：一种方法包括在可编程缓冲器处接收输入时钟信号。该方法还包括对来自可编程缓冲器的输出信号进行滤波以产生具有电压电平的滤波信号，其中电压电平指示输出信号的占空比。该方法还包括将电压电平与参考电压进行比较。该方法还包括修改可编程缓冲器的至少一个操作参数以调整输出信号的占空比。

10. 发明申请

US20130082744A1 Apparatus to Implement Symmetric Single-Ended Termination in Differential Voltage-Mode Drivers 有权
标题翻译：在差分电压模式驱动器中实现对称单端终止的装置
公开(公告)号：US20130082744A1
公开(公告)日：2013-04-04
申请号：US13248485
申请日：2011-09-29
申请人： Cheng Zhong , Vannam Dang , Miao Li , Fares K. Maarouf , Tirdad Sowlati
发明人： Cheng Zhong , Vannam Dang , Miao Li , Fares K. Maarouf , Tirdad Sowlati
IPC分类号： H03K3/00
CPC分类号： H04L25/0274 , H04L25/0278
摘要： A differential voltage mode driver for implementing symmetric single ended termination includes an output driver circuitry having a predefined termination impedance. The differential voltage mode driver also includes an output driver replica having independently controlled first and second portions. The first and second portions are independently controlled to establish a substantially equal on-resistance of the first and the second portions. The output driver replica controls the predefined termination impedance of the output driver circuitry.
摘要翻译：用于实现对称单端终端的差分电压模式驱动器包括具有预定义的终端阻抗的输出驱动器电路。差分电压模式驱动器还包括具有独立控制的第一和第二部分的输出驱动器副本。独立地控制第一和第二部分以建立第一和第二部分的基本相等的导通电阻。输出驱动器副本控制输出驱动器电路的预定终止阻抗。

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