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1. 发明申请

US20080290924A1 METHOD AND APPARATUS FOR PROGRAMMABLE DELAY HAVING FINE DELAY RESOLUTION 审中-公开
标题翻译：具有精细延迟分辨率的可编程延迟的方法和装置
公开(公告)号：US20080290924A1
公开(公告)日：2008-11-27
申请号：US12116516
申请日：2008-05-07
申请人： Jason Gonzalez , Harry H. Dang , Vannam Dang
发明人： Jason Gonzalez , Harry H. Dang , Vannam Dang
IPC分类号： H03H11/26
CPC分类号： H03K5/131 , H03K2005/00058 , H03K2005/00234
摘要： An programmable delay apparatus includes a first delay stage having a delay cell which includes a passive network, where the first delay stage is capable of providing a first time delay. The apparatus further includes a second delay stage which includes a plurality of delay cells, where each delay cell is capable of providing a second time delay which is larger than the first time delay. A method for delaying an input signal includes receiving a delay select command based upon the desired time delay, establishing a circuit path which includes at least one delay element, selected from a plurality of delay cells, according to the delay select command, wherein at least one of the plurality of delay cells includes a delay element which comprises a passive network.
摘要翻译：可编程延迟装置包括具有包括无源网络的延迟单元的第一延迟级，其中第一延迟级能够提供第一时间延迟。该装置还包括第二延迟级，其包括多个延迟单元，其中每个延迟单元能够提供大于第一时间延迟的第二时间延迟。一种用于延迟输入信号的方法包括基于所需的时间延迟接收延迟选择命令，根据延迟选择命令建立包括从多个延迟单元中选择的至少一个延迟元件的电路，其中至少所述多个延迟单元中的一个包括包括无源网络的延迟元件。

2. 发明授权

US08390314B2 Method of half-bit pre-emphasis for multi-level signal 有权
标题翻译：半电平信号的半位预加重方法
公开(公告)号：US08390314B2
公开(公告)日：2013-03-05
申请号：US13006451
申请日：2011-01-14
申请人： Harry H. Dang , Vannam Dang
发明人： Harry H. Dang , Vannam Dang
IPC分类号： H03K19/003
CPC分类号： H04L25/03834
摘要： Methods and apparatus for improving transmission channel efficiency are provided. In an example, a digital signal is received. A leading portion of a bit in the digital signal is pre-emphasized. The received digital signal is modulated with a pre-emphasis signal to pre-emphasize a leading portion of the bit in the digital signal. The pre-emphasis signal provides pre-emphasis substantially when a clock is high and the received digital signal transitions. The pre-emphasis signal does not provide pre-emphasis when the received digital signal is low or the received digital signal is unchanged. The pre-emphasized digital signal is then transmitted via the transmission channel. In an example, the received digital signal us a pulse-amplitude modulated multilevel signal.
摘要翻译：提供了改善传输通道效率的方法和装置。在一个示例中，接收数字信号。预先强调数字信号中的位的前导部分。接收到的数字信号用预加重信号进行调制，以预先强调数字信号中位的前导部分。预加重信号基本上在时钟为高并且所接收的数字信号转变时提供预加重。当接收的数字信号为低或接收的数字信号不变时，预加重信号不提供预加重。然后通过传输信道传输预先强调的数字信号。在一个例子中，接收到的数字信号是脉冲幅度调制多电平信号。

3. 发明申请

US20120182043A1 Method of Half-Bit Pre-Emphasis for Multi-Level Signal 有权
标题翻译：半电平信号的半位预加重方法
公开(公告)号：US20120182043A1
公开(公告)日：2012-07-19
申请号：US13006451
申请日：2011-01-14
申请人： Harry H. Dang , Vannam Dang
发明人： Harry H. Dang , Vannam Dang
IPC分类号： H03K19/003
CPC分类号： H04L25/03834
摘要： Methods and apparatus for improving transmission channel efficiency are provided. In an example, a digital signal is received. A leading portion of a bit in the digital signal is pre-emphasized. The received digital signal is modulated with a pre-emphasis signal to pre-emphasize a leading portion of the bit in the digital signal. The pre-emphasis signal provides pre-emphasis substantially when a clock is high and the received digital signal transitions. The pre-emphasis signal does not provide pre-emphasis when the received digital signal is low or the received digital signal is unchanged. The pre-emphasized digital signal is then transmitted via the transmission channel. In an example, the received digital signal us a pulse-amplitude modulated multilevel signal.
摘要翻译：提供了改善传输通道效率的方法和装置。在一个示例中，接收数字信号。预先强调数字信号中的位的前导部分。接收到的数字信号用预加重信号进行调制，以预先强调数字信号中位的前导部分。预加重信号基本上在时钟为高并且所接收的数字信号转变时提供预加重。当接收的数字信号为低或接收的数字信号不变时，预加重信号不提供预加重。然后通过传输信道传输预先强调的数字信号。在一个例子中，接收到的数字信号是脉冲幅度调制多电平信号。

4. 发明申请

US20110291703A1 Method and Apparatus to Sterialize Parallel Data Input Values 有权
标题翻译：平行数据输入值的方法和装置
公开(公告)号：US20110291703A1
公开(公告)日：2011-12-01
申请号：US12789566
申请日：2010-05-28
申请人： Chulkyu Lee , Harry H. Dang , Abhay S. Dixit
发明人： Chulkyu Lee , Harry H. Dang , Abhay S. Dixit
IPC分类号： H03K19/096 , G06F17/50 , H03K19/20
CPC分类号： H03K19/096 , G06F17/50 , H03K19/20 , H03M9/00
摘要： A method and apparatus to serialize parallel data input values is disclosed. In a particular embodiment, a method of serializing parallel data input values includes receiving multiple data input values in parallel at an input tier of a selection circuit, where the input tier includes multiple combinatorial gate multiplexers. The method further includes selecting an output value at an output tier of the selection circuit, where the output tier includes at least one combinatorial gate multiplexer.
摘要翻译：公开了串行化并行数据输入值的方法和装置。在特定实施例中，串行化并行数据输入值的方法包括在选择电路的输入层处并行地接收多个数据输入值，其中输入层包括多个组合门多路复用器。该方法还包括在选择电路的输出层选择输出值，其中输出层包括至少一个组合门多路复用器。

5. 发明授权

US08405426B2 Method and apparatus to serialize parallel data input values 有权
标题翻译：串行化并行数据输入值的方法和装置
公开(公告)号：US08405426B2
公开(公告)日：2013-03-26
申请号：US12789566
申请日：2010-05-28
申请人： Chulkyu Lee , Harry H. Dang , Abhay S. Dixit
发明人： Chulkyu Lee , Harry H. Dang , Abhay S. Dixit
IPC分类号： H03K19/00
CPC分类号： H03K19/096 , G06F17/50 , H03K19/20 , H03M9/00
摘要： A method and apparatus to serialize parallel data input values is disclosed. In a particular embodiment, a method of serializing parallel data input values includes receiving multiple data input values in parallel at an input tier of a selection circuit, where the input tier includes multiple combinatorial gate multiplexers. The method further includes selecting an output value at an output tier of the selection circuit, where the output tier includes at least one combinatorial gate multiplexer.
摘要翻译：公开了串行化并行数据输入值的方法和装置。在特定实施例中，串行化并行数据输入值的方法包括在选择电路的输入层并行地接收多个数据输入值，其中输入层包括多个组合门多路复用器。所述方法还包括在所述选择电路的输出层选择输出值，其中所述输出层包括至少一个组合门多路复用器。

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