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1. 发明申请

US20140157021A1 ENFORCING A POWER CONSUMPTION DUTY CYCLE IN A PROCESSOR 有权
标题翻译：执行处理器中的功耗周期
公开(公告)号：US20140157021A1
公开(公告)日：2014-06-05
申请号：US13997295
申请日：2012-11-30
申请人： Ankush Varma , Krishnakanth Sistla , Martin T. Rowland , Brian J. Griffith , Viktor D. Vogman , Joseph R. Doucette , Eric J. Dehaemer , Vivek Garg , Chris Poirier , Jeremy J. Shrall , Avinash N. Ananthakrishnan , Stephen H. Gunther
发明人： Ankush Varma , Krishnakanth Sistla , Martin T. Rowland , Brian J. Griffith , Viktor D. Vogman , Joseph R. Doucette , Eric J. Dehaemer , Vivek Garg , Chris Poirier , Jeremy J. Shrall , Avinash N. Ananthakrishnan , Stephen H. Gunther
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/06 , G06F1/324 , G06F8/4432 , Y02D10/126
摘要： In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个核心，每个核心各自独立地执行指令，多个图形引擎各自独立地执行图形操作; 以及功率控制单元，其耦合到所述多个核以控制所述处理器的功率消耗，其中所述功率控制单元包括功率偏移控制逻辑，以将所述处理器的功率消耗水平限制在高于限定功率极限以上工作周期的占空比部分。描述和要求保护其他实施例。

2. 发明申请

US20150241949A1 MECHANISM TO PROVIDE WORKLOAD AND CONFIGURATION-AWARE DETERMINISTIC PERFORMANCE FOR MICROPROCESSORS 有权
标题翻译：为微处理器提供工作负载和配置 - 确定性能的机制
公开(公告)号：US20150241949A1
公开(公告)日：2015-08-27
申请号：US14697541
申请日：2015-04-27
申请人： Ankush Varma , Krishnakanth V. Sistla , Martin T. Rowland , Chris Poirier , Eric J. Dehaemer , Avinash N. Ananthakrishnan , Jeremy J. Shrall , Xiuting C. Man , Stephen H. Gunther , Krishna K. Rangan , Devadatta V. Bodas , Don Soltis , Hang T. Nguyen , Cyprian W. Woo , Thi Dang
发明人： Ankush Varma , Krishnakanth V. Sistla , Martin T. Rowland , Chris Poirier , Eric J. Dehaemer , Avinash N. Ananthakrishnan , Jeremy J. Shrall , Xiuting C. Man , Stephen H. Gunther , Krishna K. Rangan , Devadatta V. Bodas , Don Soltis , Hang T. Nguyen , Cyprian W. Woo , Thi Dang
IPC分类号： G06F1/32 , G06F1/20
CPC分类号： G06F1/3243 , G06F1/206 , G06F1/28 , G06F1/3206 , Y02D10/152
摘要： One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.
摘要翻译：装置的一个实施例包括具有处理器和裸片上非易失性存储资源的半导体芯片。片上非易失性存储器可以为处理器的相同性能状态的不同配置和处理器的使用情况存储不同的适当的性能相关信息。

3. 发明授权

US09037840B2 Mechanism to provide workload and configuration-aware deterministic performance for microprocessors 有权
标题翻译：为微处理器提供工作负载和配置感知确定性性能的机制
公开(公告)号：US09037840B2
公开(公告)日：2015-05-19
申请号：US13538546
申请日：2012-06-29
申请人： Ankush Varma , Krishnakanth V. Sistla , Martin T. Rowland , Chris Poirier , Eric J. Dehaemer , Avinash N. Ananthakrishnan , Jeremy J. Shrall , Xiuting C. Man , Stephen H. Gunther , Krishna K. Rangan , Devadatta V. Bodas , Don Soltis , Hang T. Nguyen , Cyprian W. Woo , Thi Dang
发明人： Ankush Varma , Krishnakanth V. Sistla , Martin T. Rowland , Chris Poirier , Eric J. Dehaemer , Avinash N. Ananthakrishnan , Jeremy J. Shrall , Xiuting C. Man , Stephen H. Gunther , Krishna K. Rangan , Devadatta V. Bodas , Don Soltis , Hang T. Nguyen , Cyprian W. Woo , Thi Dang
IPC分类号： G06F15/177 , G06F1/00 , G06F1/32 , G06F1/20
CPC分类号： G06F1/3243 , G06F1/206 , G06F1/28 , G06F1/3206 , Y02D10/152
摘要： An apparatus that includes a semiconductor chip having a processor and an on-die non-volatile storage resource is described. The on-die non volatile storage is to store different, appropriate performance related information for different configurations and/or usage cases of the processor for a same performance state of the processor.
摘要翻译：描述了包括具有处理器和裸片上非易失性存储资源的半导体芯片的装置。在线非易失性存储器是为处理器的相同性能状态存储用于处理器的不同配置和/或使用情况的不同的适当的性能相关信息。

4. 发明申请

US20140006761A1 MECHANISM TO PROVIDE WORKLOAD AND CONFIGURATION-AWARE DETERMINISTIC PERFORMANCE FOR MICROPROCESSORS 有权
标题翻译：为微处理器提供工作负载和配置 - 确定性能的机制
公开(公告)号：US20140006761A1
公开(公告)日：2014-01-02
申请号：US13538546
申请日：2012-06-29
申请人： Ankush Varma , Krishnakanth V. Sistla , Martin T. Rowland , Chris Poirier , Eric J. Dehaemer , Avinash N. Ananthakrishnan , Jeremy J. Shrall , Xiuting C. Man , Stephen H. Gunther , Krishna K. Rangan , Devadatta V. Bodas , Don Soltis , Hang T. Nguyen , Cyprian W. Woo , Thi Dang
发明人： Ankush Varma , Krishnakanth V. Sistla , Martin T. Rowland , Chris Poirier , Eric J. Dehaemer , Avinash N. Ananthakrishnan , Jeremy J. Shrall , Xiuting C. Man , Stephen H. Gunther , Krishna K. Rangan , Devadatta V. Bodas , Don Soltis , Hang T. Nguyen , Cyprian W. Woo , Thi Dang
IPC分类号： G06F1/00 , G06F9/00
CPC分类号： G06F1/3243 , G06F1/206 , G06F1/28 , G06F1/3206 , Y02D10/152
摘要： An apparatus that includes a semiconductor chip having a processor and an on-die non-volatile storage resource is described. The on-die non volatile storage is to store different, appropriate performance related information for different configurations and/or usage cases of the processor for a same performance state of the processor.
摘要翻译：描述了包括具有处理器和裸片上非易失性存储资源的半导体芯片的装置。在线非易失性存储器是为处理器的相同性能状态存储用于处理器的不同配置和/或使用情况的不同的适当的性能相关信息。

5. 发明申请

US20140173297A1 Performing Frequency Coordination In A Multiprocessor System 有权
标题翻译：在多处理器系统中执行频率协调
公开(公告)号：US20140173297A1
公开(公告)日：2014-06-19
申请号：US13716712
申请日：2012-12-17
申请人： Ankush Varma , Krishnakanth V. Sistla , Ian M. Steiner , Vivek Garg , Chris Poirier , Martin T. Rowland
发明人： Ankush Varma , Krishnakanth V. Sistla , Ian M. Steiner , Vivek Garg , Chris Poirier , Martin T. Rowland
IPC分类号： G06F1/26
CPC分类号： G06F1/324 , G06F1/32 , G06F1/3203 , G06F1/329 , G06F9/5044 , G06F9/505 , G06F13/00 , G06F15/17325 , G06T1/20 , Y02D10/126
摘要： In an embodiment, a processor includes a core to execute instructions, uncore logic coupled to the core, and a power controller to control a power consumption level. The power controller is configured to determine an activity level of the processor and responsive to this level, to generate a request for communication to a second processor coupled to the processor to request frequency coordination between the processors. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括执行指令的核心，耦合到核心的非逻辑逻辑以及用于控制功耗水平的功率控制器。功率控制器被配置为确定处理器的活动级别并响应于该级别，以产生与耦合到处理器的第二处理器通信以请求处理器之间的频率协调的请求。描述和要求保护其他实施例。

6. 发明申请

US20140281445A1 PROCESSOR HAVING FREQUENCY OF OPERATION INFORMATION FOR GUARANTEED OPERATION UNDER HIGH TEMPERATURE EVENTS 有权
标题翻译：具有运行信息频率的处理器，用于在高温事件下进行有担保的操作
公开(公告)号：US20140281445A1
公开(公告)日：2014-09-18
申请号：US13843855
申请日：2013-03-15
申请人： Ankush Varma , Robin A. Steinbrecher , Susan F. Smith , Sandeep Ahuja , Vivek Garg , Tessil Thomas , Krishnakanth V. Sistla , Chris Poirier , Martin Mark T. Rowland
发明人： Ankush Varma , Robin A. Steinbrecher , Susan F. Smith , Sandeep Ahuja , Vivek Garg , Tessil Thomas , Krishnakanth V. Sistla , Chris Poirier , Martin Mark T. Rowland
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/20 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/16
摘要： A processor is described having a semiconductor chip having non volatile storage circuitry. The non volatile storage circuitry has information identifying a maximum operational frequency of the processor at which the processor's operation is guaranteed for an ambient temperature that corresponds to an extreme thermal event.
摘要翻译：描述了具有具有非易失性存储电路的半导体芯片的处理器。非易失性存储电路具有识别处理器的最大工作频率的信息，在该处理器处理器的操作被保证对应于极端热事件的环境温度。

7. 发明授权

US09436254B2 Method and apparatus for per core performance states 有权
标题翻译：每个核心性能状态的方法和装置
公开(公告)号：US09436254B2
公开(公告)日：2016-09-06
申请号：US13976682
申请日：2012-03-13
申请人： Malini K. Bhandaru , Eric J. Dehaemer , Samuel W. Ho , Scott P. Bobholz , Chris Poirier
发明人： Malini K. Bhandaru , Eric J. Dehaemer , Samuel W. Ho , Scott P. Bobholz , Chris Poirier
IPC分类号： G06F1/26 , G06F1/32 , G06F9/50
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F1/329 , G06F1/3296 , G06F9/5094 , Y02D10/152 , Y02D10/22 , Y02D10/24
摘要： A method and apparatus for per core performance states in a processor. Per Core Performance States (PCPS) refer to the parallel operating of individual cores at different voltage and/frequency points. In one embodiment of the invention, the processor has a plurality of processing cores and a power control module that is coupled with each of the plurality of processing cores. The power control module facilitates each processing core to operate at a different performance state from the other processing cores. By allowing its cores to have per core performance state configuration, the processor is able to reduce its power consumption and increase its performance.
摘要翻译：一种处理器中每个核心性能状态的方法和装置。每个核心性能状态（PCPS）是指在不同的电压和/频率点对各个内核的并行运行。在本发明的一个实施例中，处理器具有多个处理核心和与多个处理核心中的每一个耦合的功率控制模块。功率控制模块便于每个处理核心在与其他处理核心不同的性能状态下工作。通过允许其内核具有每个核心性能状态配置，处理器能够降低其功耗并提高其性能。

8. 发明授权

US06789186B1 Method and apparatus to reduce penalty of microcode lookup 失效
标题翻译：减少微码查找罚款的方法和装置
公开(公告)号：US06789186B1
公开(公告)日：2004-09-07
申请号：US09507038
申请日：2000-02-18
申请人： Russell C. Brockmann , Kevin David Safford , Jane Wang , Chris Poirier
发明人： Russell C. Brockmann , Kevin David Safford , Jane Wang , Chris Poirier
IPC分类号： G06G900
CPC分类号： G06F9/3804 , G06F9/30174
摘要： A method and apparatus are provided for improving the rate at which macroinstructions are transformed into corresponding microinstructions. Encoding is added to a microcode storage device. The encoding indicates that a microinstruction flow will end in a determined number of cycles. The number of cycles is determined by the number of canceled instructions in a processing pipeline that would be introduced if no flow length prediction was used. For flow lengths less than a determined number of cycles, a hint bit is used in an entry point structure. For flow lengths greater than a determined length, a hint bit is encoded at a third line from an end of the microinstruction flow. Using this method, flows of any length can be hinted. Furthermore, flows that do not originate from the entry point structure can also be hinted. The method reduces the number of hint bits that are needed in the entry point structure and provides for better prediction.
摘要翻译：提供了一种方法和装置，用于提高宏指令转换成相应微指令的速率。编码被添加到微代码存储设备中。编码指示微指令流将以确定的周期数结束。循环数由在不使用流量长度预测的情况下将被引入的处理流水线中的取消指令的数量来确定。对于小于一定数量的循环的流量长度，在入口点结构中使用提示位。对于大于确定长度的流量长度，提示位在微指令流的末尾的第三行编码。使用这种方法，可以暗示任何长度的流。此外，也可以暗示不源于入口点结构的流。该方法减少了入口点结构中所需的提示位的数量，并提供了更好的预测。

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