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1. 发明授权

US08255198B2 Method and structure to develop a test program for semiconductor integrated circuits 有权
标题翻译：制定半导体集成电路测试程序的方法和结构
公开(公告)号：US08255198B2
公开(公告)日：2012-08-28
申请号：US12748317
申请日：2010-03-26
申请人： Ramachandran Krishnaswamy , Harsanjeet Singh , Ankan Pramanick , Mark Elston , Leon Chen , Toshiaki Adachi , Yoshihumi Tahara
发明人： Ramachandran Krishnaswamy , Harsanjeet Singh , Ankan Pramanick , Mark Elston , Leon Chen , Toshiaki Adachi , Yoshihumi Tahara
IPC分类号： G06F17/50 , G06G7/62 , G01R31/00 , G01R31/14
CPC分类号： G01R31/3183 , G01R31/318307 , G01R31/318342 , G01R31/31907
摘要： Test program development for a semiconductor test system, such as automated test equipment (ATE), using object-oriented constructs is described. The invention provides a method for describing test system resources, test system configuration, module configuration, test sequence, test plan, test condition, test pattern, and timing information in general-purpose object-oriented constructs, e.g., C++ objects and classes. In particular, the modularity of program development is suitable for developing test programs for an open architecture semiconductor test system.
摘要翻译：描述了使用面向对象构造的半导体测试系统（例如自动化测试设备（ATE））的测试程序开发。本发明提供了一种用于描述例如C ++对象和类的通用面向对象结构中的测试系统资源，测试系统配置，模块配置，测试顺序，测试计划，测试条件，测试模式和定时信息的方法。特别地，程序开发的模块化适用于开发开放式架构半导体测试系统的测试程序。

2. 发明申请

US20080010524A1 TEST EMULATOR, TEST MODULE EMULATOR AND RECORD MEDIUM STORING PROGRAM THEREIN 审中-公开
标题翻译：测试仿真器，测试模块仿真器和记录媒体存储程序
公开(公告)号：US20080010524A1
公开(公告)日：2008-01-10
申请号：US11860469
申请日：2007-09-24
申请人： Shinsaku Higashi , Seiji Ichiyoshi , Ankan Pramanick , Mark Elston , Leon Chen , Robert Sauer , Ramachandran Krishnaswamy , Harsanjeet Singh , Toshiaki Adachi , Yoshihumi Tahara
发明人： Shinsaku Higashi , Seiji Ichiyoshi , Ankan Pramanick , Mark Elston , Leon Chen , Robert Sauer , Ramachandran Krishnaswamy , Harsanjeet Singh , Toshiaki Adachi , Yoshihumi Tahara
IPC分类号： H02H3/05
CPC分类号： G01R31/3183 , G01R31/318307 , G01R31/318342 , G01R31/31907
摘要： There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of the test signal generating timings output by the timing alignment section to generate the test signal in simulation in the cycle time corresponding to the test signal generating timing.
摘要翻译：提供了一种用于模拟测试装置的测试仿真器，该测试装置包括用于将测试信号分别提供给被测试器件的多个测试模块，包括：多个测试模块仿真部分，用于仿真基于不同的测试信号生成测试信号的多个测试模块循环，用于仿真用于控制被测设备的测试的控制装置的控制仿真部分，用于产生测试信号产生定时的同步仿真部分，多个测试模块仿真部分中的每个测试信号产生定时部分将在其中生成测试信号基于来自控制仿真部分的指令，对应于测试模块仿真部分的周期时间的模拟定时对准部分，用于对准由同步仿真部分按时间顺序产生的多个测试信号产生定时，并且通过一个以及用于引起测试模块仿真部分的调度部分对应于由定时对准部分输出的测试信号产生定时之一，以在对应于测试信号产生定时的周期时间中在仿真中产生测试信号。

3. 发明申请

US20050154551A1 Method and structure to develop a test program for semiconductor integrated circuits 有权
标题翻译：制定半导体集成电路测试程序的方法和结构
公开(公告)号：US20050154551A1
公开(公告)日：2005-07-14
申请号：US10918714
申请日：2004-08-13
申请人： Ankan Pramanick , Mark Elston , Ramachandran Krishnaswamy , Toshiaki Adachi
发明人： Ankan Pramanick , Mark Elston , Ramachandran Krishnaswamy , Toshiaki Adachi
IPC分类号： G01R31/3183 , G01R31/319 , G06F11/263 , G06F19/00
CPC分类号： G01R31/3183 , G01R31/318307 , G01R31/318314 , G01R31/318342 , G01R31/31907 , G06F11/263
摘要： A method for developing a test program for a semiconductor test system is disclosed. The method includes describing a test plan file in a test program language (TPL), where the test plan file describes at least one test of the test program, describing a test class file in a system program language (SPL) and a corresponding pre-header file of the test class file in the TPL, where the test class file describes an implementation of the at least one test of the test program, and generating the test program using the test plan file, the test class file, and the pre-header file.
摘要翻译：公开了一种用于开发半导体测试系统的测试程序的方法。该方法包括以测试程序语言（TPL）描述测试计划文件，其中测试计划文件描述测试程序的至少一个测试，描述系统程序语言（SPL）的测试类文件和相应的预测文件 TPL中的测试类文件的头文件，其中测试类文件描述测试程序的至少一个测试的实现，以及使用测试计划文件，测试类文件和预测文件生成测试程序，头文件。

4. 发明申请

US20080016396A1 TEST EMULATOR, TEST MODULE EMULATOR AND RECORD MEDIUM STORING PROGRAM THEREIN 审中-公开
公开(公告)号：US20080016396A1
公开(公告)日：2008-01-17
申请号：US11860437
申请日：2007-09-24
申请人： Shinsaku Higashi , Seiji Ichiyoshi , Ankan Pramanick , Mark Elston , Leon Chen , Robert Sauer , Ramachandran Krishnaswamy , Harsanjeet Singh , Toshiaki Adachi , Yoshihumi Tahara
发明人： Shinsaku Higashi , Seiji Ichiyoshi , Ankan Pramanick , Mark Elston , Leon Chen , Robert Sauer , Ramachandran Krishnaswamy , Harsanjeet Singh , Toshiaki Adachi , Yoshihumi Tahara
IPC分类号： G06F11/25
CPC分类号： G01R31/3183 , G01R31/318307 , G01R31/318342 , G01R31/31907
摘要： There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of the test signal generating timings output by the timing alignment section to generate the test signal in simulation in the cycle time corresponding to the test signal generating timing.

5. 发明授权

US07197417B2 Method and structure to develop a test program for semiconductor integrated circuits 有权
标题翻译：制定半导体集成电路测试程序的方法和结构
公开(公告)号：US07197417B2
公开(公告)日：2007-03-27
申请号：US10918714
申请日：2004-08-13
申请人： Ankan Pramanick , Mark Elston , Ramachandran Krishnaswamy , Toshiaki Adachi
发明人： Ankan Pramanick , Mark Elston , Ramachandran Krishnaswamy , Toshiaki Adachi
IPC分类号： G06F19/00
CPC分类号： G01R31/3183 , G01R31/318307 , G01R31/318314 , G01R31/318342 , G01R31/31907 , G06F11/263
摘要： A method for developing a test program for a semiconductor test system is disclosed. The method includes describing a test plan file in a test program language (TPL), where the test plan file describes at least one test of the test program, describing a test class file in a system program language (SPL) and a corresponding pre-header file of the test class file in the TPL, where the test class file describes an implementation of the at least one test of the test program, and generating the test program using the test plan file, the test class file, and the pre-header file.
摘要翻译：公开了一种用于开发半导体测试系统的测试程序的方法。该方法包括以测试程序语言（TPL）描述测试计划文件，其中测试计划文件描述测试程序的至少一个测试，描述系统程序语言（SPL）的测试类文件和相应的预测文件 TPL中的测试类文件的头文件，其中测试类文件描述测试程序的至少一个测试的实现，以及使用测试计划文件，测试类文件和预测文件生成测试程序，头文件。

6. 发明申请

US20050039079A1 Test emulator, test module emulator, and record medium storing program therein 审中-公开
标题翻译：测试仿真器，测试模块仿真器和其中的记录介质存储程序
公开(公告)号：US20050039079A1
公开(公告)日：2005-02-17
申请号：US10814603
申请日：2004-03-31
申请人： Shinsaku Higashi , Seiji Ichiyoshi , Ankan Pramanick , Mark Elston , Leon Chen , Robert Sauer , Ramachandran Krishnaswamy , Harsanjeet Singh , Toshiaki Adachi , Yoshihumi Tahara
发明人： Shinsaku Higashi , Seiji Ichiyoshi , Ankan Pramanick , Mark Elston , Leon Chen , Robert Sauer , Ramachandran Krishnaswamy , Harsanjeet Singh , Toshiaki Adachi , Yoshihumi Tahara
IPC分类号： G01R31/3183 , G01R31/319 , H02H3/05
CPC分类号： G01R31/3183 , G01R31/318307 , G01R31/318342 , G01R31/31907
摘要： There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of the test signal generating timings output by the timing alignment section to generate the test signal in simulation in the cycle time corresponding to the test signal generating timing.
摘要翻译：提供了一种用于模拟测试装置的测试仿真器，该测试装置包括用于将测试信号分别提供给被测试器件的多个测试模块，包括：多个测试模块仿真部分，用于仿真基于不同的测试信号生成测试信号的多个测试模块循环，用于仿真用于控制被测设备的测试的控制装置的控制仿真部分，用于产生测试信号产生定时的同步仿真部分，多个测试模块仿真部分中的每个测试信号产生定时部分将在其中生成测试信号基于来自控制仿真部分的指令，对应于测试模块仿真部分的周期时间的模拟定时对准部分，用于对准由同步仿真部分按时间顺序产生的多个测试信号产生定时，并且通过一个以及用于引起测试模块仿真部分的调度部分对应于由定时对准部分输出的测试信号产生定时之一，以在对应于测试信号产生定时的周期时间中在仿真中产生测试信号。

7. 发明授权

US08082541B2 Method and system for performing installation and configuration management of tester instrument modules 失效
标题翻译：用于执行测试仪器模块的安装和配置管理的方法和系统
公开(公告)号：US08082541B2
公开(公告)日：2011-12-20
申请号：US11100109
申请日：2005-04-05
申请人： Ankan Pramanick , Jim Hanrahan , Mark Elston , Toshiaki Adachi , Leon L. Chen
发明人： Ankan Pramanick , Jim Hanrahan , Mark Elston , Toshiaki Adachi , Leon L. Chen
IPC分类号： G06F9/44 , G06F9/45 , G06F9/445
CPC分类号： G06F9/44 , G01R31/3183 , G01R31/318307 , G01R31/318314 , G01R31/319 , G01R31/31907 , G01R31/31908 , G06F8/61
摘要： A method for managing multiple hardware test module versions, software components, and tester operating system (TOS) versions in a modular test system is disclosed. The method includes installing the TOS versions compatible with the modular test system in an archive and installing vendor software components corresponding to the hardware test module versions in the archive. The method further includes creating system profiles for describing vendor software components corresponding to the hardware test module versions and the TOS versions, selecting a system profile for the modular test system, where the system profile includes a set of compatible vendor software components and a selected TOS for testing a particular hardware test module version, and activating the selected TOS on the modular test system.
摘要翻译：公开了一种在模块化测试系统中管理多个硬件测试模块版本，软件组件和测试仪操作系统（TOS）版本的方法。该方法包括将与模块化测试系统兼容的TOS版本安装在归档中，并安装与存档中的硬件测试模块版本对应的供应商软件组件。该方法还包括创建用于描述对应于硬件测试模块版本和TOS版本的供应商软件组件的系统简档，为模块化测试系统选择系统简档，其中系统简档包括一组兼容供应商软件组件和选择的TOS 用于测试特定硬件测试模块版本，并激活模块化测试系统上选定的TOS。

8. 发明授权

US07209851B2 Method and structure to develop a test program for semiconductor integrated circuits 有权
标题翻译：制定半导体集成电路测试程序的方法和结构
公开(公告)号：US07209851B2
公开(公告)日：2007-04-24
申请号：US10918513
申请日：2004-08-13
申请人： Harsanjeet Singh , Ankan Pramanick , Mark Elston , Yoshifumi Tahara , Toshiaki Adachi
发明人： Harsanjeet Singh , Ankan Pramanick , Mark Elston , Yoshifumi Tahara , Toshiaki Adachi
IPC分类号： G06F19/00
CPC分类号： G01R31/31907 , G01R31/3183 , G01R31/318307 , G01R31/318342
摘要： A method for managing a pattern object file in a modular test system is disclosed. The method includes providing a modular test system, where the modular test system comprises a system controller for controlling at least one site controller, and where the at least one site controller controls at least one test module and its corresponding device under test (DUT). The method further includes creating an object file management framework for establishing a standard interface between vendor-supplied pattern compilers and the modular test system, receiving a pattern source file, creating a pattern object metafile based on the pattern source file using the object file management framework, and testing the device under test through the test module using the pattern object metafile.
摘要翻译：公开了一种用于管理模块化测试系统中的模式对象文件的方法。该方法包括提供模块化测试系统，其中模块化测试系统包括用于控制至少一个站点控制器的系统控制器，并且其中至少一个站点控制器控制至少一个测试模块及其对应的被测设备（DUT）。该方法还包括创建用于在供应商提供的模式编译器和模块化测试系统之间建立标准接口的对象文件管理框架，接收模式源文件，使用目标文件管理框架基于模式源文件创建模式对象元文件，并使用模式对象元文件通过测试模块测试被测设备。

9. 发明申请

US20050154550A1 Method and structure to develop a test program for semiconductor integrated circuits 有权
标题翻译：制定半导体集成电路测试程序的方法和结构
公开(公告)号：US20050154550A1
公开(公告)日：2005-07-14
申请号：US10918513
申请日：2004-08-13
申请人： Harsanjeet Singh , Ankan Pramanick , Mark Elston , Yoshifumi Tahara , Toshiaki Adachi
发明人： Harsanjeet Singh , Ankan Pramanick , Mark Elston , Yoshifumi Tahara , Toshiaki Adachi
IPC分类号： G01R31/3183 , G01R31/319 , G06F11/26 , G06F17/50 , G06F19/00
CPC分类号： G01R31/31907 , G01R31/3183 , G01R31/318307 , G01R31/318342
摘要： A method for managing a pattern object file in a modular test system is disclosed. The method includes providing a modular test system, where the modular test system comprises a system controller for controlling at least one site controller, and where the at least one site controller controls at least one test module and its corresponding device under test (DUT). The method further includes creating an object file management framework for establishing a standard interface between vendor-supplied pattern compilers and the modular test system, receiving a pattern source file, creating a pattern object metafile based on the pattern source file using the object file management framework, and testing the device under test through the test module using the pattern object metafile.
摘要翻译：公开了一种用于管理模块化测试系统中的模式对象文件的方法。该方法包括提供模块化测试系统，其中模块化测试系统包括用于控制至少一个站点控制器的系统控制器，并且其中至少一个站点控制器控制至少一个测试模块及其对应的被测设备（DUT）。该方法还包括创建用于在供应商提供的模式编译器和模块化测试系统之间建立标准接口的对象文件管理框架，接收模式源文件，使用目标文件管理框架基于模式源文件创建模式对象元文件，并使用模式对象元文件通过测试模块测试被测设备。

10. 发明授权

US07543200B2 Method and system for scheduling tests in a parallel test system 失效
标题翻译：并行测试系统中调度测试的方法和系统
公开(公告)号：US07543200B2
公开(公告)日：2009-06-02
申请号：US11062244
申请日：2005-02-17
申请人： Ankan Pramanick , Toshiaki Adachi , Mark Elston
发明人： Ankan Pramanick , Toshiaki Adachi , Mark Elston
IPC分类号： G01R31/28 , G11C29/00 , G06F11/00
CPC分类号： G01R31/31907 , G01R31/31912
摘要： An efficient and low-cost method for testing multiple DUTs in a parallel test system is disclosed. In one embodiment, a method for scheduling tests in a parallel test system having at least two devices-under-test (DUTs) coupled to a test controller through one or more vendor hardware modules includes receiving a test plan comprising a plurality of tests arranged in a predetermined test flow, where the predetermined test flow comprises a plurality of tests arranged in a directed graph and each test is arranged as a vertex in the directed graph, determining a test execution schedule in accordance with the test plan at runtime, where the test execution schedule identifies a set of next tests to be executed according to current states of the at least two DUTs and where the set of next tests include different tests to be performed on different DUTs, and testing the at least two DUTs using the test execution schedule.
摘要翻译：公开了一种用于在并行测试系统中测试多个DUT的有效且低成本的方法。在一个实施例中，一种用于在具有通过一个或多个供应商硬件模块耦合到测试控制器的至少两个被测设备（DUT））的并行测试系统中调度测试的方法包括：接收包括多个测试预定测试流程，其中预定测试流程包括以有向图形布置的多个测试，并且每个测试被布置为有向图中的顶点，根据运行时的测试计划确定测试执行计划，其中测试执行时间表根据所述至少两个DUT的当前状态识别要执行的一组下一个测试，并且下一个测试的集合包括将在不同的DUT上执行的不同的测试，以及使用测试执行时间表测试所述至少两个DUT 。

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