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1. 发明授权

US08674418B2 Method and apparatus for achieving galvanic isolation in package having integral isolation medium 有权
标题翻译：用于在具有整体隔离介质的包装中实现电隔离的方法和装置
公开(公告)号：US08674418B2
公开(公告)日：2014-03-18
申请号：US13214069
申请日：2011-08-19
申请人： Anindya Poddar , Vijaylaxmi Khanolkar , Ashok S. Prabhu , Peter Johnson
发明人： Anindya Poddar , Vijaylaxmi Khanolkar , Ashok S. Prabhu , Peter Johnson
IPC分类号： H01L31/062 , H01L21/70 , H01L23/552
CPC分类号： H01F17/0013 , H01F27/32 , H01F27/36 , H01F2017/008
摘要： An inductor device having an improved galvanic isolation layer arranged between a pair of coil and methods of its construction are described.
摘要翻译：描述了一种具有布置在一对线圈之间的改进的电隔离层和其构造方法的电感器件。

2. 发明授权

US06933597B1 Spacer with passive components for use in multi-chip modules 有权
标题翻译：带无源元件的隔板用于多芯片模块
公开(公告)号：US06933597B1
公开(公告)日：2005-08-23
申请号：US10192173
申请日：2002-07-09
申请人： Anindya Poddar , Ashok S. Prabhu
发明人： Anindya Poddar , Ashok S. Prabhu
IPC分类号： H01L23/02 , H01L23/552 , H01L25/065
CPC分类号： H01L25/0657 , H01L23/552 , H01L24/48 , H01L2224/16 , H01L2224/48091 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06572 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for providing passive circuit functions in a multi-chip module and the multi-chip modules that result from incorporating these function is disclosed. Passive components such as resistors, capacitors and inductors are fabricated on or within a non-conductive spacer. The spacer is then placed between two active semiconductor dies and coupled electrically to either one or both of the dies. In this manner, area of the active dies that would normally have to be used for such passive components is freed for other uses and the spacer, which was already required in multi-chip modules, is endowed with extra functionality. In another embodiment, one or both surfaces of the spacer are coated with a conductive metal and the passive components are located within the spacer. In this embodiment, the spacer provides electromagnetic interference protection between the active dies.
摘要翻译：公开了一种在多芯片模块中提供无源电路功能的方法以及由这些功能引入的多芯片模块。诸如电阻器，电容器和电感器的无源部件制造在非导电间隔件上或内部。然后将间隔物放置在两个有源半导体管芯之间，并且电连接到裸片之一或两者。以这种方式，通常必须用于这种无源部件的有源管芯的面积被释放用于其他用途，并且已经在多芯片模块中已经需要的间隔件具有额外的功能。在另一个实施例中，间隔物的一个或两个表面涂覆有导电金属，并且无源部件位于间隔物内。在该实施例中，间隔件在活动管芯之间提供电磁干扰保护。

3. 发明申请

US20080241991A1 GANG FLIPPING FOR FLIP-CHIP PACKAGING 审中-公开
标题翻译：襟翼包装的缉拿
公开(公告)号：US20080241991A1
公开(公告)日：2008-10-02
申请号：US11691428
申请日：2007-03-26
申请人： Anindya Poddar , Jaime A. Bayan , Ashok S. Prabhu , Will K. Wong
发明人： Anindya Poddar , Jaime A. Bayan , Ashok S. Prabhu , Will K. Wong
IPC分类号： H01L21/00
CPC分类号： H01L23/49548 , H01L21/561 , H01L24/13 , H01L24/81 , H01L24/97 , H01L2221/68354 , H01L2224/11822 , H01L2224/16245 , H01L2224/81001 , H01L2224/81011 , H01L2224/81801 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2224/81 , H01L2224/0401
摘要： An improved method and apparatus for packaging integrated circuits are described. More particularly, a method and apparatus for use in securing a plurality of integrated circuit dice to a lead frame panel are described. Each integrated circuit die includes an active surface having a multiplicity of solder bumps. The lead frame panel includes an array of device areas, each including a plurality of leads. The method includes positioning a plurality of dice into designated positions on a carrier such that the active surfaces of the dice are facing upwards. The carrier includes a carrier frame including an associated array of carrier device areas. A lead frame panel may be positioned over the carrier such that the solder bumps on the active surfaces of the dice are adjacent and in contact with the associated leads of the associated device areas.
摘要翻译：描述了用于封装集成电路的改进的方法和装置。更具体地，描述了用于将多个集成电路芯片固定到引线框架面板的方法和装置。每个集成电路管芯包括具有多个焊料凸点的有源表面。引线框架面板包括一组设备区域，每个设备区域包括多个引线。该方法包括将多个骰子定位在载体上的指定位置，使得骰子的活动表面朝上。载体包括载体框架，其包括相关的载体装置区域阵列。引线框架面板可以定位在载体上方，使得骰子的有效表面上的焊料凸块相邻并与相关联的器件区域的相关引线接触。

4. 发明授权

US08283760B1 Lead frame interconnect scheme with high power density 有权
标题翻译：具有高功率密度的引线框架互连方案
公开(公告)号：US08283760B1
公开(公告)日：2012-10-09
申请号：US12760365
申请日：2010-04-14
申请人： Ken Pham , Anindya Poddar , Ashok S. Prabhu
发明人： Ken Pham , Anindya Poddar , Ashok S. Prabhu
IPC分类号： H01L29/94 , H01L23/48
CPC分类号： H01L23/49572 , H01L23/4951 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0401 , H01L2224/05073 , H01L2224/05124 , H01L2224/05155 , H01L2224/05166 , H01L2224/05567 , H01L2224/05573 , H01L2224/05624 , H01L2224/05644 , H01L2224/1134 , H01L2224/13144 , H01L2224/16245 , H01L2224/16503 , H01L2224/17107 , H01L2224/73204 , H01L2224/81191 , H01L2224/81203 , H01L2224/81207 , H01L2224/81439 , H01L2924/00013 , H01L2924/00014 , H01L2924/01029 , H01L2924/01327 , H01L2924/1306 , H01L2924/15747 , H01L2924/181 , H01L2224/81206 , H01L2924/049 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/05552
摘要： An integrated circuit package configured to incorporate a lead frame and methods for its making are is described. The package comprising an IC with aluminum bond pads in communication with circuitry of the die with lead frame with silver bond pads. The package having gold bumps bonded between the aluminum bond pad of the die and the silver bond pad of the lead frame. The package including an encapsulant envelope and including various materials and bond pad structures and constructed in a manner formed by thermosonically or thermocompressionally bonding the gold balls to the bond pads. Also, disclosed are methods of making the package.
摘要翻译：描述了一种被构造成结合引线框的集成电路封装及其制造方法。该封装包括具有铝接合焊盘的IC，其与具有银键焊盘的引线框的管芯的电路连通。该封装在金属模的铝合金焊盘与引线框的银焊盘之间焊接有金凸点。所述包装包括密封剂封套并且包括各种材料和接合焊盘结构，并且以通过热熔或热压粘合金球到接合焊盘形成的方式构造。此外，公开了制造包装的方法。

5. 发明授权

US07102209B1 Substrate for use in semiconductor manufacturing and method of making same 有权
标题翻译：用于半导体制造的基板及其制造方法
公开(公告)号：US07102209B1
公开(公告)日：2006-09-05
申请号：US10650325
申请日：2003-08-27
申请人： Jaime Bayan , Ashok S. Prabhu , Fred Drummond
发明人： Jaime Bayan , Ashok S. Prabhu , Fred Drummond
IPC分类号： H01L23/495
CPC分类号： H01L23/3107 , H01L23/49548 , H01L23/49861 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/97 , H01L2224/32245 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2224/83 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A lead-frame based substrate panel for use in semiconductor packaging is described. The substrate panel includes a lead-frame panel having at least one array of device areas. Each device area has a plurality of contacts. The lead-frame panel is filled with a dielectric material to form a relatively rigid substrate panel that can be used for packaging integrated circuits. The top surface of the dielectric material is typically substantially coplanar with the top surface of the lead-frame panel, and the bottom surface of the dielectric material is typically substantially coplanar with the bottom surface of the lead-frame panel.
摘要翻译：描述了用于半导体封装的基于引线框架的基板面板。衬底面板包括具有至少一个器件区域阵列的引线框架面板。每个设备区域具有多个触点。引线框板填充有电介质材料以形成可用于封装集成电路的相对刚性的基板。电介质材料的顶表面通常与引线框架板的顶表面基本上共面，并且电介质材料的底表面通常与引线框架板的底表面基本上共面。

6. 发明授权

US07087986B1 Solder pad configuration for use in a micro-array integrated circuit package 有权
标题翻译：焊盘配置用于微阵列集成电路封装
公开(公告)号：US07087986B1
公开(公告)日：2006-08-08
申请号：US10871313
申请日：2004-06-18
申请人： Jaime A. Bayan , Ashok S. Prabhu , Shaw Wei Lee
发明人： Jaime A. Bayan , Ashok S. Prabhu , Shaw Wei Lee
IPC分类号： H01L23/495 , H01L23/04
CPC分类号： H01L23/49541 , H01L23/3107 , H01L23/49503 , H01L23/49548 , H01L24/48 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48463 , H01L2224/48465 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A solder pad configuration for use in an IC package is described. Various embodiments of the invention describe IC packages, lead-frames, or substrate panels configured with generally noncircular solder pads at their bottom surfaces. The noncircular shapes allow for greater surface area than circular solder pads having diameters equal to a major dimension of the noncircular shapes, while maintaining the same metal-to-metal clearance between the pads and adjacent leads. This increased surface area provides for stronger and more reliable solder joints.
摘要翻译：描述了用于IC封装中的焊盘配置。本发明的各种实施例描述了在其底表面上配置有大致非圆形焊盘的IC封装，引线框架或基板。非圆形形状允许比具有等于非圆形形状的主要尺寸的直径的圆形焊盘更大的表面积，同时在焊盘和相邻引线之间保持相同的金属与金属间隙。这种增加的表面积提供了更坚固和更可靠的焊点。

7. 发明授权

US06364089B1 Multi-station rotary die handling device 有权
标题翻译：多工位旋转模具处理装置
公开(公告)号：US06364089B1
公开(公告)日：2002-04-02
申请号：US09549241
申请日：1999-12-10
申请人： Inderjit Singh , Jaime A. Bayan , Hem Takiar , Ashok S. Prabhu
发明人： Inderjit Singh , Jaime A. Bayan , Hem Takiar , Ashok S. Prabhu
IPC分类号： B65G4724
CPC分类号： H01L21/67132 , B65G47/848 , H01L21/6838
摘要： The invention relates to apparatus and methods for semiconductor device handling. In one aspect, the invention relates to a rotary flipper including a wheel having a plurality of stations. A semiconductor device is placed within a first station in a first orientation. While the semiconductor device is held, the wheel portion of the rotary flipper rotates and the next station receives another semiconductor device. When the first station is in an unloading position, the semiconductor device is released. At this point, the semiconductor device is oriented in a second position. In one aspect, the semiconductor device is released into a cavity of a tape and reel. In another aspect, vacuum pressure is applied to hold the die. In one embodiment, the invention relates to a semiconductor device handling apparatus and apparatus that includes of a rotary semiconductor device flipper.
摘要翻译：本发明涉及半导体器件处理的装置和方法。一方面，本发明涉及一种包括具有多个站的车轮的旋转导板。半导体器件以第一取向放置在第一工位内。在保持半导体器件的同时，旋转推板的轮部分旋转并且下一个站接收另一个半导体器件。当第一站处于卸载位置时，半导体器件被释放。此时，半导体器件被定向在第二位置。在一个方面，半导体器件被释放到带和卷的空腔中。另一方面，施加真空压力以保持模具。在一个实施例中，本发明涉及一种包括旋转半导体器件引脚的半导体器件处理装置和装置。

8. 发明授权

US07259460B1 Wire bonding on thinned portions of a lead-frame configured for use in a micro-array integrated circuit package 有权
标题翻译：引线框架的薄部分上的引线接合被配置为用于微阵列集成电路封装
公开(公告)号：US07259460B1
公开(公告)日：2007-08-21
申请号：US10871218
申请日：2004-06-18
申请人： Jamie A. Bayan , Ashok S. Prabhu , Chan Peng Yeen , Hasfiza Ramley , Santhiran S/O Nadarajah
发明人： Jamie A. Bayan , Ashok S. Prabhu , Chan Peng Yeen , Hasfiza Ramley , Santhiran S/O Nadarajah
IPC分类号： H01L23/34
CPC分类号： H01L23/3107 , H01L21/568 , H01L23/49541 , H01L23/49548 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Aspects of the invention recite wire bonding on thinned portions of a lead-frame that is configured for use in an IC package. A harder lead-frame material, improved adhesive tape, and various structural features of the lead-frame itself, in various combinations or subcombinations, facilitate the attachment of wire bonds to thinned areas of the lead-frame. This eliminates the need for supports placed directly under the bond sites, removing unwanted conductive areas on the outer surface of an IC package.
摘要翻译：本发明的各个方面在配置用于IC封装中的引线框架的薄部分上引用引线接合。引线框架本身以各种组合或子组合的较硬的引线框架材料，改进的胶带以及各种结构特征有助于将引线键连接到引线框架的变薄区域。这消除了对直接位于结合位置下方的支撑物的需要，从而去除IC封装外表面上的不需要的导电区域。

9. 发明授权

US07186588B1 Method of fabricating a micro-array integrated circuit package 有权
标题翻译：制造微阵列集成电路封装的方法
公开(公告)号：US07186588B1
公开(公告)日：2007-03-06
申请号：US10871188
申请日：2004-06-18
申请人： Jaime A. Bayan , Santhiran S/O Nadarajah , Chan Chee Ling , Ashok S. Prabhu , Hasfiza Ramley , Chan Peng Yeen
发明人： Jaime A. Bayan , Santhiran S/O Nadarajah , Chan Chee Ling , Ashok S. Prabhu , Hasfiza Ramley , Chan Peng Yeen
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L24/83 , H01L21/568 , H01L23/4951 , H01L23/4952 , H01L23/49548 , H01L23/544 , H01L24/27 , H01L24/29 , H01L24/48 , H01L24/73 , H01L24/85 , H01L24/97 , H01L2223/54486 , H01L2224/274 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2224/83191 , H01L2224/83856 , H01L2224/85 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of fabricating a micro-array IC package is recited. A wafer has a B-stageable adhesive applied, and the wafer is diced. The individual dice are applied to a lead-frame via their adhesive, and wirebonded to associated leads. The lead-frame is then encapsulated, and solder connectors are applied. The lead-frame is then singulated to produce a plurality of lead-frame based micro-array packages. The process thus allows lead-frame based manufacturing methods to be employed in the production of BGA-type packages, allowing such packages to be produced faster and more efficiently.
摘要翻译：列举了制造微阵列IC封装的方法。晶片具有可施加的B级粘合剂，并且晶片被切割。单个骰子通过其粘合剂施加到引线框架，并且引线键合到相关联的引线。然后封装引线框架，并应用焊接连接器。引线框架然后被分割以产生多个基于引线框架的微阵列封装。因此，该方法允许基于引线框架的制造方法用于生产BGA型封装，从而允许更快更有效地制造这种封装。

10. 发明申请

US20120326287A1 DC/DC CONVERTOR POWER MODULE PACKAGE INCORPORATING A STACKED CONTROLLER AND CONSTRUCTION METHODOLOGY 审中-公开
标题翻译： DC / DC转换器电源模块包装堆叠控制器和构造方法
公开(公告)号：US20120326287A1
公开(公告)日：2012-12-27
申请号：US13170017
申请日：2011-06-27
申请人： Rajeev Joshi , Jaime A. Bayan , Ashok S. Prabhu
发明人： Rajeev Joshi , Jaime A. Bayan , Ashok S. Prabhu
IPC分类号： H01L23/495 , H05K1/11 , H01L21/82
CPC分类号： H01L23/49575 , H01L21/56 , H01L23/3107 , H01L23/49524 , H01L23/49548 , H01L23/49562 , H01L24/36 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L27/0688 , H01L27/088 , H01L2224/05554 , H01L2224/40091 , H01L2224/40095 , H01L2224/40245 , H01L2224/48247 , H01L2224/49109 , H01L2224/73221 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/07802 , H01L2924/1306 , H01L2924/181 , H05K1/0296 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/37099
摘要： Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.
摘要翻译：描述了用于实现小尺寸功率转换器和小尺寸功率转换器装置的有效制造的方法和系统。

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