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1. 发明授权

US08518765B1 Aqua regia and hydrogen peroxide HCl combination to remove Ni and NiPt residues 有权
标题翻译：水王和过氧化氢HCl组合去除Ni和NiPt残留物
公开(公告)号：US08518765B1
公开(公告)日：2013-08-27
申请号：US13489244
申请日：2012-06-05
申请人： Anh Duong , Clemens Fitz , Olov Karlsson
发明人： Anh Duong , Clemens Fitz , Olov Karlsson
IPC分类号： H01L21/336
CPC分类号： C11D11/0047 , C11D7/04 , C11D7/08 , C11D7/265 , H01L21/02057 , H01L21/02068 , H01L21/28052 , H01L21/324 , H01L21/6704 , H01L29/4975 , H01L29/66477 , H01L29/665 , H01L29/66568
摘要： A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The SC2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate.
摘要翻译：公开了一种在镍铂硅化过程中从半导体衬底中清除残余物的方法，包括多步残渣清洗，包括将底物暴露于王水溶液中，然后暴露于含有盐酸和过氧化氢的溶液中。 SC2溶液可以与剩余的铂残留物进一步反应，使其更易溶于水溶液，从而从基底表面溶解。

2. 发明授权

US08513117B2 Process to remove Ni and Pt residues for NiPtSi applications 有权
标题翻译：去除NiPtSi应用的Ni和Pt残留物的工艺
公开(公告)号：US08513117B2
公开(公告)日：2013-08-20
申请号：US13296444
申请日：2011-11-15
申请人： Anh Duong , Sean Barstow , Clemens Fitz , John Foster , Olov Karlsson , Bei Li , James Mavrinac
发明人： Anh Duong , Sean Barstow , Clemens Fitz , John Foster , Olov Karlsson , Bei Li , James Mavrinac
IPC分类号： H01L21/44
CPC分类号： H01L21/02068 , H01L21/28052 , H01L21/28518 , H01L29/665
摘要： The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Embodiments of the invention provide a multi-step cleaning process, comprising exposing the substrate to a nitric acid solution after a first anneal, followed by an aqua regia solution after a second anneal. The substrate can be optionally exposed to a hydrochloric acid solution afterward to completely remove any remaining platinum residues.
摘要翻译：本发明公开了一种在镍铂硅化过程中清除半导体衬底的残留物的方法。本发明的实施方案提供了一种多步骤清洗方法，包括在第一次退火之后将基底暴露于硝酸溶液，然后在第二次退火之后暴露于王水溶液中。可以将底物任选地暴露于盐酸溶液中以完全除去任何剩余的铂残余物。

3. 发明申请

US20130122671A1 PROCESS TO REMOVE Ni AND Pt RESIDUES FOR NiPtSi APPLICATIONS 有权
标题翻译：去除NiPtSi应用的Ni和Pt残留物的工艺
公开(公告)号：US20130122671A1
公开(公告)日：2013-05-16
申请号：US13296444
申请日：2011-11-15
申请人： Anh Duong , Sean Barstow , Clemens Fitz , John Foster , Olov Karlsson , Bei Li , James Mavrinac
发明人： Anh Duong , Sean Barstow , Clemens Fitz , John Foster , Olov Karlsson , Bei Li , James Mavrinac
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L21/02068 , H01L21/28052 , H01L21/28518 , H01L29/665
摘要： The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Embodiments of the invention provide a multi-step cleaning process, comprising exposing the substrate to a nitric acid solution after a first anneal, followed by an aqua regia solution after a second anneal. The substrate can be optionally exposed to a hydrochloric acid solution afterward to completely remove any remaining platinum residues.
摘要翻译：本发明公开了一种在镍铂硅化过程中清除半导体衬底的残留物的方法。本发明的实施方案提供了一种多步骤清洗方法，包括在第一次退火之后将基底暴露于硝酸溶液，然后在第二次退火之后暴露于王水溶液中。可以将底物任选地暴露于盐酸溶液中以完全除去任何剩余的铂残余物。

4. 发明申请

US20130058559A1 METHOD AND APPARATUS FOR CHARACTERIZING DISCONTINUITIES IN SEMICONDUCTOR DEVICES 有权
标题翻译：用于表征半导体器件中不连续性的方法和装置
公开(公告)号：US20130058559A1
公开(公告)日：2013-03-07
申请号：US13223998
申请日：2011-09-01
申请人： Jochen Rinderknecht , Inka Richter , Clemens Fitz
发明人： Jochen Rinderknecht , Inka Richter , Clemens Fitz
IPC分类号： G06K9/00
CPC分类号： G06T7/0006 , G06T2207/10061 , G06T2207/30148
摘要： An approach is provided for characterizing discontinuities in semiconductor devices, for example in a metal silicide. An image of an integrated circuit is caused, at least in part, to be received. The image is analyzed for at least one discontinuity in the integrated circuit structure. A relative measure of the at least one discontinuity is determined in comparison to the integrated circuit structure based on analyzing the image.
摘要翻译：提供了用于表征半导体器件中的不连续性的方法，例如在金属硅化物中。至少部分地引起集成电路的图像被接收。分析图像在集成电路结构中的至少一个不连续性。与基于分析图像的集成电路结构相比，确定至少一个不连续性的相对度量。

5. 发明申请

US20120220086A1 METHODS FOR FABRICATING A CMOS INTEGRATED CIRCUIT HAVING A DUAL STRESS LAYER (DSL) 有权
标题翻译：用于制造具有双应力层（DSL）的CMOS集成电路的方法
公开(公告)号：US20120220086A1
公开(公告)日：2012-08-30
申请号：US13034902
申请日：2011-02-25
申请人： Peter Baars , Marco Lepper , Clemens Fitz
发明人： Peter Baars , Marco Lepper , Clemens Fitz
IPC分类号： H01L21/8238 , H01L21/30
CPC分类号： H01L21/823807 , H01L21/3105 , H01L21/823814 , H01L21/823864
摘要： Methods are provided for fabricating a CMOS integrated circuit having a dual stress layer without NiSi hole formation. One method includes depositing a tensile stress layer overlying a semiconductor substrate. A portion of the tensile stress layer is removed, leaving a remaining portion, before applying a curing radiation. A curing radiation is then applied to the remaining portion; and a compressive stress layer is deposited overlying the semiconductor substrate and the remaining portion.
摘要翻译：提供了用于制造具有不具有NiSi孔形成的双应力层的CMOS集成电路的方法。一种方法包括沉积覆盖半导体衬底的拉伸应力层。在施加固化辐射之前，去除一部分拉伸应力层，留下剩余部分。然后将固化辐射施加到剩余部分; 并且沉积覆盖半导体衬底和剩余部分的压应力层。

6. 发明授权

US08008729B2 Integrated circuit with a contact structure including a portion arranged in a cavity of a semiconductor structure 有权
标题翻译：具有包括布置在半导体结构的空腔中的部分的接触结构的集成电路
公开(公告)号：US08008729B2
公开(公告)日：2011-08-30
申请号：US12251864
申请日：2008-10-15
申请人： Werner Graf , Clemens Fitz
发明人： Werner Graf , Clemens Fitz
IPC分类号： H01L23/522
CPC分类号： H01L21/743 , H01L21/823418 , H01L21/823475 , H01L23/485 , H01L29/66636 , H01L2221/1063 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a contact structure with a buried first and a protruding second portion. The buried first portion is arranged in a cavity formed in a semiconductor structure and is in direct contact with the semiconductor structure. The protruding second portion is arranged above the main surface of the semiconductor structure and in direct contact with a conductive structure that is spaced apart from or separated from the main surface of the semiconductor structure. An insulator structure is arranged below and in direct contact with the contact structure.
摘要翻译：集成电路包括具有埋入的第一和突出的第二部分的接触结构。掩埋的第一部分布置在形成于半导体结构中并与半导体结构直接接触的空腔中。突出的第二部分布置在半导体结构的主表面上方，并且与与半导体结构的主表面间隔开或分离的导电结构直接接触。绝缘体结构布置在接触结构的下方并直接接触。

7. 发明申请

US20130234213A1 NISI REWORK PROCEDURE TO REMOVE PLATINUM RESIDUALS 有权
标题翻译： NISI淘汰淘汰计划废除残留物
公开(公告)号：US20130234213A1
公开(公告)日：2013-09-12
申请号：US13415492
申请日：2012-03-08
申请人： Sivakumar KUMARASAMY , Clemens Fitz , Markus Lenski , Jochen Poth , Kristin Schupke
发明人： Sivakumar KUMARASAMY , Clemens Fitz , Markus Lenski , Jochen Poth , Kristin Schupke
IPC分类号： H01L21/66 , H01L29/68
CPC分类号： H01L21/28518 , H01L22/12 , H01L22/20
摘要： The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing a rework including applying SPM at a temperature of 130° C. in a SWC tool, if Pt residue is detected. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer, annealing the Ni removed Ni/Pt layer, removing unreacted Pt from the annealed Ni removed Ni/Pt layer, analyzing the Pt removed Ni/Pt layer for unreacted Pt residue, and if unreacted Pt residue is detected, applying SPM to the Pt removed Ni/Pt layer in a SWC tool. The SPM may be applied to the Pt removed Ni'/Pt layer at a temperature of 130° C.
摘要翻译：如果检测到Pt残留物，则通过执行包括在SWC工具中在130℃的温度下施加SPM的返工来减少形成含Pt的NiSi后剩余的Pt残余物的量。实施例包括在半导体衬底上沉积一层Ni / Pt，退火沉积的Ni / Pt层，从退火的Ni / Pt层去除未反应的Ni，退火Ni去除的Ni / Pt层，从退火的Ni中除去未反应的Pt Ni / Pt层，分析未去除Pt残留物的Pt去除Ni / Pt层，如果检测到未反应的Pt残留物，则在SWC工具中将Pt施加到去除的Pt / Ni层上。可以在130℃的温度下将SPM施加到Pt去除的Ni'/ Pt层上

8. 发明申请

US20130052819A1 Methods of Forming Metal Silicide Regions on Semiconductor Devices Using Different Temperatures 有权
标题翻译：在使用不同温度的半导体器件上形成金属硅化物区域的方法
公开(公告)号：US20130052819A1
公开(公告)日：2013-02-28
申请号：US13218089
申请日：2011-08-25
申请人： Thilo Scheiper , Peter Javorka , Stefan Flachowsky , Clemens Fitz
发明人： Thilo Scheiper , Peter Javorka , Stefan Flachowsky , Clemens Fitz
IPC分类号： H01L21/3205
CPC分类号： H01L21/28518 , H01L21/823814 , H01L21/823835
摘要： Disclosed herein are various methods of forming metal silicide regions on semiconductor devices by using different temperatures during the silicidation processes. In one example, the method includes forming a plurality of N-doped source/drain regions and a plurality of P-doped source/drain regions in a semiconducting substrate and performing a first heating process at a first temperature to initially form a first metal silicide region in each of the P-doped source/drain regions. The method further includes performing a second heating process at a second temperature to initially form a second metal silicide region in each of the N-doped source/drain regions, wherein the second temperature is less than the first temperature and performing a third heating process at a third temperature to complete the formation of the first and second metal silicide regions, wherein the third temperature is greater than the first temperature.
摘要翻译：本文公开了通过在硅化工艺期间使用不同温度在半导体器件上形成金属硅化物区域的各种方法。在一个示例中，该方法包括在半导体衬底中形成多个N掺杂源极/漏极区域和多个P掺杂的源极/漏极区域，并且在第一温度下执行第一加热过程以最初形成第一金属硅化物每个P掺杂源/漏区中的区域。该方法还包括在第二温度下执行第二加热处理，以在N掺杂源极/漏极区域中的每一个中初始形成第二金属硅化物区域，其中第二温度小于第一温度，并且在第三温度以完成所述第一和第二金属硅化物区域的形成，其中所述第三温度大于所述第一温度。

9. 发明授权

US08293605B2 Methods for fabricating a CMOS integrated circuit having a dual stress layer (DSL) 有权
标题翻译：制造具有双重应力层（DSL）的CMOS集成电路的方法
公开(公告)号：US08293605B2
公开(公告)日：2012-10-23
申请号：US13034902
申请日：2011-02-25
申请人： Peter Baars , Marco Lepper , Clemens Fitz
发明人： Peter Baars , Marco Lepper , Clemens Fitz
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/3105 , H01L21/823814 , H01L21/823864
摘要： Methods are provided for fabricating a CMOS integrated circuit having a dual stress layer without NiSi hole formation. One method includes depositing a tensile stress layer overlying a semiconductor substrate. A portion of the tensile stress layer is removed, leaving a remaining portion, before applying a curing radiation. A curing radiation is then applied to the remaining portion; and a compressive stress layer is deposited overlying the semiconductor substrate and the remaining portion.
摘要翻译：提供了用于制造具有不具有NiSi孔形成的双应力层的CMOS集成电路的方法。一种方法包括沉积覆盖半导体衬底的拉伸应力层。在施加固化辐射之前，去除一部分拉伸应力层，留下剩余部分。然后将固化辐射施加到剩余部分; 并且沉积覆盖半导体衬底和剩余部分的压应力层。

10. 发明授权

US08835318B2 HNO3 single wafer clean process to strip nickel and for MOL post etch 有权
标题翻译： HNO3单晶片清洁工艺，用于剥离镍和MOL后蚀刻
公开(公告)号：US08835318B2
公开(公告)日：2014-09-16
申请号：US13414946
申请日：2012-03-08
申请人： Clemens Fitz , Jochen Poth , Kristin Schupke
发明人： Clemens Fitz , Jochen Poth , Kristin Schupke
IPC分类号： H01L21/283 , H01L23/532
CPC分类号： H01L21/02068 , H01L21/28518 , H01L21/76829 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Ni and Pt residuals are eliminated by replacing an SPM cleaning process with application of HNO3 in an SWC tool. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer by applying HNO3 to the annealed Ni/Pt layer in an SWC tool, annealing the Ni removed Ni/Pt layer, and removing unreacted Pt from the annealed Ni removed Ni/Pt layer. Embodiments include forming first and second gate electrodes on a substrate, spacers on opposite sides of each gate electrode, and Pt-containing NiSi on the substrate adjacent each spacer, etching back the spacers, forming a tensile strain layer over the first gate electrode, applying a first HNO3 in an SWC tool, forming a compressive strain layer over the second gate electrode, and applying a second HNO3 in an SWC tool.
摘要翻译：通过在SWC工具中应用HNO3代替SPM清洗工艺，可以消除Ni和Pt残留物。实施例包括在半导体衬底上沉积一层Ni / Pt，对沉积的Ni / Pt层进行退火，通过在SWC工具中对退火的Ni / Pt层施加HNO 3，从退火的Ni / Pt层去除未反应的Ni，退火Ni 去除Ni / Pt层，并从退火的Ni去除的Ni / Pt层去除未反应的Pt。实施例包括在基板上形成第一和第二栅极电极，在每个栅电极的相对侧上形成间隔物，并在邻近每个间隔物的衬底上形成含Pt的NiSi，蚀刻间隔物，在第一栅电极上形成拉伸应变层，在SWC工具中的第一HNO 3，在第二栅电极上形成压应变层，并在SWC工具中施加第二HNO 3。

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