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1. 发明授权

US08293605B2 Methods for fabricating a CMOS integrated circuit having a dual stress layer (DSL) 有权
标题翻译：制造具有双重应力层（DSL）的CMOS集成电路的方法
公开(公告)号：US08293605B2
公开(公告)日：2012-10-23
申请号：US13034902
申请日：2011-02-25
申请人： Peter Baars , Marco Lepper , Clemens Fitz
发明人： Peter Baars , Marco Lepper , Clemens Fitz
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/3105 , H01L21/823814 , H01L21/823864
摘要： Methods are provided for fabricating a CMOS integrated circuit having a dual stress layer without NiSi hole formation. One method includes depositing a tensile stress layer overlying a semiconductor substrate. A portion of the tensile stress layer is removed, leaving a remaining portion, before applying a curing radiation. A curing radiation is then applied to the remaining portion; and a compressive stress layer is deposited overlying the semiconductor substrate and the remaining portion.
摘要翻译：提供了用于制造具有不具有NiSi孔形成的双应力层的CMOS集成电路的方法。一种方法包括沉积覆盖半导体衬底的拉伸应力层。在施加固化辐射之前，去除一部分拉伸应力层，留下剩余部分。然后将固化辐射施加到剩余部分; 并且沉积覆盖半导体衬底和剩余部分的压应力层。

2. 发明申请

US20120220086A1 METHODS FOR FABRICATING A CMOS INTEGRATED CIRCUIT HAVING A DUAL STRESS LAYER (DSL) 有权
标题翻译：用于制造具有双应力层（DSL）的CMOS集成电路的方法
公开(公告)号：US20120220086A1
公开(公告)日：2012-08-30
申请号：US13034902
申请日：2011-02-25
申请人： Peter Baars , Marco Lepper , Clemens Fitz
发明人： Peter Baars , Marco Lepper , Clemens Fitz
IPC分类号： H01L21/8238 , H01L21/30
CPC分类号： H01L21/823807 , H01L21/3105 , H01L21/823814 , H01L21/823864
摘要： Methods are provided for fabricating a CMOS integrated circuit having a dual stress layer without NiSi hole formation. One method includes depositing a tensile stress layer overlying a semiconductor substrate. A portion of the tensile stress layer is removed, leaving a remaining portion, before applying a curing radiation. A curing radiation is then applied to the remaining portion; and a compressive stress layer is deposited overlying the semiconductor substrate and the remaining portion.
摘要翻译：提供了用于制造具有不具有NiSi孔形成的双应力层的CMOS集成电路的方法。一种方法包括沉积覆盖半导体衬底的拉伸应力层。在施加固化辐射之前，去除一部分拉伸应力层，留下剩余部分。然后将固化辐射施加到剩余部分; 并且沉积覆盖半导体衬底和剩余部分的压应力层。

3. 发明授权

US08883586B2 Mol insitu Pt rework sequence 有权
标题翻译：莫尔实验Pt返修序列
公开(公告)号：US08883586B2
公开(公告)日：2014-11-11
申请号：US13079492
申请日：2011-04-04
申请人： Peter Baars , Marco Lepper , Uwe Kahler , Vivien Schroeder
发明人： Peter Baars , Marco Lepper , Uwe Kahler , Vivien Schroeder
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/3213 , H01L21/285 , H01L29/66 , H01L29/78 , H01L21/02
CPC分类号： H01L21/2855 , H01L21/02068 , H01L21/28518 , H01L21/32134 , H01L29/4958 , H01L29/665 , H01L29/6653 , H01L29/7843
摘要： The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing an O2 flash while shaping gate spacers, and then cleaning and applying a second application of Aqua Regia. Embodiments include sputter depositing a layer of Ni/Pt on a semiconductor substrate, annealing the Ni/Pt layer, wet stripping unreacted Ni, annealing the Ni stripped Ni/Pt layer, stripping unreacted Pt from the annealed Ni/Pt layer, e.g., with Aqua Regia, treating the Pt stripped Ni/Pt layer with an oxygen plasma, cleaning the Ni/Pt layer, and stripping unreacted Pt from the cleaned Ni/Pt layer, e.g., with a second application of Aqua Regia.
摘要翻译：在形成含Pt的NiSi之后剩余的Pt残余物的量通过在形成浇口间隔件的同时进行O2闪光，然后清洗并应用Aqua Regia的第二次应用来减少。实施例包括在半导体衬底上溅射沉积Ni / Pt层，退火Ni / Pt层，湿剥离未反应的Ni，退火Ni剥离的Ni / Pt层，从退火的Ni / Pt层剥离未反应的Pt，例如， Aqua Regia，用氧等离子体处理Pt剥离的Ni / Pt层，清洁Ni / Pt层，以及从清洁的Ni / Pt层剥离未反应的Pt，例如，通过第二次应用Aqua Regia。

4. 发明授权

US08673696B2 SOI semiconductor device comprising a substrate diode with reduced metal silicide leakage 有权
标题翻译： SOI半导体器件包括具有减少的金属硅化物泄漏的衬底二极管
公开(公告)号：US08673696B2
公开(公告)日：2014-03-18
申请号：US13397345
申请日：2012-02-15
申请人： Peter Baars , Frank Jakubowski , Jens Heinrich , Marco Lepper , Jana Schlott , Kai Frohberg
发明人： Peter Baars , Frank Jakubowski , Jens Heinrich , Marco Lepper , Jana Schlott , Kai Frohberg
IPC分类号： H01L21/00 , H01L21/425 , H01L21/44
CPC分类号： H01L27/1207 , H01L21/84 , H01L29/665 , H01L29/7833
摘要： When forming substrate diodes in SOI devices, superior diode characteristics may be preserved by providing an additional spacer element in the substrate opening and/or by using a superior contact patterning regime on the basis of a sacrificial fill material. In both cases, integrity of a metal silicide in the substrate diode may be preserved, thereby avoiding undue deviations from the desired ideal diode characteristics. In some illustrative embodiments, the superior diode characteristics may be achieved without requiring any additional lithography step.
摘要翻译：当在SOI器件中形成衬底二极管时，可以通过在衬底开口中提供附加的间隔元件和/或通过基于牺牲填充材料使用优良的接触图案化方案来保护优异的二极管特性。在这两种情况下，可以保持衬底二极管中的金属硅化物的完整性，从而避免与期望的理想二极管特性的过度偏差。在一些说明性实施例中，可以实现优异的二极管特性而不需要任何额外的光刻步骤。

5. 发明申请

US20130049124A1 MOSFET INTEGRATED CIRCUIT WITH IMPROVED SILICIDE THICKNESS UNIFORMITY AND METHODS FOR ITS MANUFACTURE 审中-公开
标题翻译：具有改进的硅酸盐厚度均匀的MOSFET集成电路及其制造方法
公开(公告)号：US20130049124A1
公开(公告)日：2013-02-28
申请号：US13223016
申请日：2011-08-31
申请人： Clemens Fitz , Stephan Waidmann , Stefan Flachowsky , Peter Baars , Rainer Giedigkeit
发明人： Clemens Fitz , Stephan Waidmann , Stefan Flachowsky , Peter Baars , Rainer Giedigkeit
IPC分类号： H01L27/088 , H01L21/3205
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/823425 , H01L29/1083 , H01L29/165 , H01L29/6659 , H01L29/7848
摘要： An MOSFET device having a Silicide layer of uniform thickness and which is substantially free of “Spotty” NiSi-type holes, and methods for its fabrication, are provided. One such method involves simultaneously depositing a metal layer (e.g. Ni) over the active and open areas of a semiconductor substrate. The depth to which some or all of the metal is transferred into the substrate is determined by thermal budget. A rapid thermal annealing process is employed to produce a NiSi layer of a uniform thickness in both the active and open areas. Upon achieving a NiSi layer of a desired thickness, the excess metal is removed from the substrate surface.
摘要翻译：具有均匀厚度并且基本上没有斑点NiSi型孔的硅化物层的MOSFET器件及其制造方法。一种这样的方法涉及在半导体衬底的有源和开放区域上同时沉积金属层（例如Ni）。一些或全部金属转移到基底中的深度由热预算确定。采用快速热退火工艺来在活性和开放区域中制备均匀厚度的NiSi层。在达到所需厚度的NiSi层时，从衬底表面去除多余的金属。

6. 发明授权

US08765586B2 Methods of forming metal silicide regions on semiconductor devices 有权
标题翻译：在半导体器件上形成金属硅化物区域的方法
公开(公告)号：US08765586B2
公开(公告)日：2014-07-01
申请号：US13331842
申请日：2011-12-20
申请人： Clemens Fitz , Peter Baars , Markus Lenski
发明人： Clemens Fitz , Peter Baars , Markus Lenski
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/76897 , H01L21/28518 , H01L21/28556 , H01L21/76814 , H01L29/41783 , H01L29/66545
摘要： Disclosed herein are various methods of forming metal silicide regions on semiconductor devices. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, performing a selective metal silicide formation process to form metal silicide regions in source/drain regions formed in or above the substrate, after forming the metal silicide regions, removing the sacrificial gate structure to define a gate opening and forming a replacement gate structure in the gate opening, the replacement gate structure comprised of at least one metal layer.
摘要翻译：本文公开了在半导体器件上形成金属硅化物区域的各种方法。在一个示例中，该方法包括在半导体衬底之上形成牺牲栅极结构，在形成金属硅化物区域之后，执行选择性金属硅化物形成工艺以形成在衬底中或上方形成的源极/漏极区域中的金属硅化物区域，牺牲栅极结构以限定栅极开口并在栅极开口中形成替代栅极结构，所述替换栅极结构由至少一个金属层组成。

7. 发明申请

US20130157450A1 Methods of Forming Metal Silicide Regions on Semiconductor Devices 有权
标题翻译：在半导体器件上形成金属硅化物区域的方法
公开(公告)号：US20130157450A1
公开(公告)日：2013-06-20
申请号：US13331842
申请日：2011-12-20
申请人： Clemens Fitz , Peter Baars , Markus Lenski
发明人： Clemens Fitz , Peter Baars , Markus Lenski
IPC分类号： H01L21/283
CPC分类号： H01L21/76897 , H01L21/28518 , H01L21/28556 , H01L21/76814 , H01L29/41783 , H01L29/66545
摘要： Disclosed herein are various methods of forming metal silicide regions on semiconductor devices. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, performing a selective metal silicide formation process to form metal silicide regions in source/drain regions formed in or above the substrate, after forming the metal silicide regions, removing the sacrificial gate structure to define a gate opening and forming a replacement gate structure in the gate opening, the replacement gate structure comprised of at least one metal layer.
摘要翻译：本文公开了在半导体器件上形成金属硅化物区域的各种方法。在一个示例中，该方法包括在半导体衬底之上形成牺牲栅极结构，在形成金属硅化物区域之后，执行选择性金属硅化物形成工艺以形成在衬底中或上方形成的源极/漏极区域中的金属硅化物区域，牺牲栅极结构以限定栅极开口并在栅极开口中形成替代栅极结构，所述替换栅极结构由至少一个金属层组成。

8. 发明申请

US20120299160A1 Method of Forming Contacts for Devices with Multiple Stress Liners 有权
标题翻译：形成具有多个应力衬垫的装置的触点的方法
公开(公告)号：US20120299160A1
公开(公告)日：2012-11-29
申请号：US13116672
申请日：2011-05-26
申请人： Peter Baars , Marco Lepper , Thilo Scheiper
发明人： Peter Baars , Marco Lepper , Thilo Scheiper
IPC分类号： H01L21/311 , H01L23/58
CPC分类号： H01L21/823807 , H01L21/823864 , H01L21/823871
摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method includes performing a first process operation to form a first etch stop layer above a first region of a semiconducting substrate where a first type of transistor device will be formed, and forming a first stress inducing layer at least above the first etch stop layer in the first region, wherein the first stress inducing layer is adapted to induce a stress in a channel region of the first type of transistor. The method further includes, after forming the first etch stop layer, performing a second process operation form a second etch stop layer above a second region of the substrate where a second type of transistor device will be formed, and forming a second stress inducing layer at least above the second etch stop layer in the second region, wherein the second stress inducing layer is adapted to induce a stress in a channel region of the second type of transistor. In one particular example, the first and second etch stop layers may have the same approximate thickness.
摘要翻译：本文公开了形成半导体器件的方法。在一个示例中，该方法包括执行第一处理操作以在半导体衬底的第一区域上方形成第一蚀刻停止层，其中将形成第一类型的晶体管器件，以及形成至少高于第一类型的第一应力诱导层所述第一区域中的所述蚀刻停止层，其中所述第一应力诱导层适于在所述第一类型晶体管的沟道区域中引起应力。该方法还包括：在形成第一蚀刻停止层之后，执行第二处理操作，形成第二蚀刻停止层，该第二蚀刻停止层位于衬底的第二区域的第二区域上方，在该第二区域将形成第二类型的晶体管器件，并且形成第二应力诱导层至少在第二区域中的第二蚀刻停止层上方，其中第二应力诱导层适于在第二类型晶体管的沟道区域中引起应力。在一个具体示例中，第一和第二蚀刻停止层可以具有相同的近似厚度。

9. 发明申请

US20120248551A1 MOL INSITU PT REWORK SEQUENCE 有权
标题翻译： MOL INSITU PT REWORK序列
公开(公告)号：US20120248551A1
公开(公告)日：2012-10-04
申请号：US13079492
申请日：2011-04-04
申请人： Peter Baars , Marco Lepper , Uwe Kahler , Vivien Schroeder
发明人： Peter Baars , Marco Lepper , Uwe Kahler , Vivien Schroeder
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L21/2855 , H01L21/02068 , H01L21/28518 , H01L21/32134 , H01L29/4958 , H01L29/665 , H01L29/6653 , H01L29/7843
摘要： The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing an O2 flash while shaping gate spacers, and then cleaning and applying a second application of Aqua Regia. Embodiments include sputter depositing a layer of Ni/Pt on a semiconductor substrate, annealing the Ni/Pt layer, wet stripping unreacted Ni, annealing the Ni stripped Ni/Pt layer, stripping unreacted Pt from the annealed Ni/Pt layer, e.g., with Aqua Regia, treating the Pt stripped Ni/Pt layer with an oxygen plasma, cleaning the Ni/Pt layer, and stripping unreacted Pt from the cleaned Ni/Pt layer, e.g., with a second application of Aqua Regia.
摘要翻译：在形成含Pt的NiSi之后剩余的Pt残余物的量通过在形成浇口间隔件的同时进行O2闪光，然后清洗并应用Aqua Regia的第二次应用来减少。实施例包括在半导体衬底上溅射沉积Ni / Pt层，退火Ni / Pt层，湿剥离未反应的Ni，退火Ni剥离的Ni / Pt层，从退火的Ni / Pt层剥离未反应的Pt，例如， Aqua Regia，用氧等离子体处理Pt剥离的Ni / Pt层，清洁Ni / Pt层，以及从清洁的Ni / Pt层剥离未反应的Pt，例如，通过第二次应用Aqua Regia。

10. 发明授权

US09023696B2 Method of forming contacts for devices with multiple stress liners 有权
标题翻译：形成具有多个应力衬垫的装置的触点的方法
公开(公告)号：US09023696B2
公开(公告)日：2015-05-05
申请号：US13116672
申请日：2011-05-26
申请人： Peter Baars , Marco Lepper , Thilo Scheiper
发明人： Peter Baars , Marco Lepper , Thilo Scheiper
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L21/823871
摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method includes performing a first process operation to form a first etch stop layer above a first region of a semiconducting substrate where a first type of transistor device will be formed, and forming a first stress inducing layer at least above the first etch stop layer in the first region, wherein the first stress inducing layer is adapted to induce a stress in a channel region of the first type of transistor. The method further includes, after forming the first etch stop layer, performing a second process operation form a second etch stop layer above a second region of the substrate where a second type of transistor device will be formed, and forming a second stress inducing layer at least above the second etch stop layer in the second region, wherein the second stress inducing layer is adapted to induce a stress in a channel region of the second type of transistor. In one particular example, the first and second etch stop layers may have the same approximate thickness.
摘要翻译：本文公开了形成半导体器件的方法。在一个示例中，该方法包括执行第一处理操作以在半导体衬底的第一区域上方形成第一蚀刻停止层，其中将形成第一类型的晶体管器件，以及形成至少高于第一类型的第一应力诱导层所述第一区域中的所述蚀刻停止层，其中所述第一应力诱导层适于在所述第一类型晶体管的沟道区域中引起应力。该方法还包括：在形成第一蚀刻停止层之后，执行第二处理操作，形成第二蚀刻停止层，该第二蚀刻停止层位于衬底的第二区域的第二区域上方，在该第二区域将形成第二类型的晶体管器件，并且形成第二应力诱导层至少在第二区域中的第二蚀刻停止层上方，其中第二应力诱导层适于在第二类型晶体管的沟道区域中引起应力。在一个具体示例中，第一和第二蚀刻停止层可以具有相同的近似厚度。

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