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1. 发明授权

US07472358B2 Method and system for outputting a sequence of commands and data described by a flowchart 有权
标题翻译：用于输出由流程图描述的命令和数据序列的方法和系统
公开(公告)号：US07472358B2
公开(公告)日：2008-12-30
申请号：US11260517
申请日：2005-10-27
申请人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
发明人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F8/66
摘要： The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A processor is generated to include the ROM, wherein the processor receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.
摘要翻译：本发明是用于输出由流程图描述的命令和数据序列的方法和系统。该方法包括以下步骤。接收描述命令和数据序列的流程图。流程图包括多个流程图符号。多个流程图符号中的每一个被分配有ROM（只读存储器）记录。分配的ROM记录存储在ROM中。产生处理器以包括ROM，其中处理器接收CLOCK信号作为输入，RESET信号，ENABLE信号和N个二进制输入x1，x2，...。。。 xN，并输出命令和数据的顺序。

2. 发明授权

US07315993B2 Verification of RRAM tiling netlist 失效
标题翻译：验证RRAM平铺网表
公开(公告)号：US07315993B2
公开(公告)日：2008-01-01
申请号：US10999468
申请日：2004-11-30
申请人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
发明人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F9/45 , G06F17/50 , G06F11/00 , G11C29/00
CPC分类号： G06F17/5022
摘要： The present invention provides a method of verification of a RRAM tiling netlist. The method may include steps as follows. Properties “memory_number”, “clock_number” and “netlist_part” of all nets and cells of a RRAM tiling netlist are set to a value 0. A boolean value 0 is assigned to all ground nets of the RRAM tiling netlist, and a boolean value 1 is assigned to all power nets of the RRAM tiling netlist. The RRAM tiling netlist is verified for each customer memory Memk, k=1, 2, . . . , N.
摘要翻译：本发明提供了一种RRAM拼接网表的验证方法。该方法可以包括以下步骤。属性RRAM平铺网表的所有网络和单元格的“memory_number”，“clock_number”和“netlist_part”被设置为0.值为0的布尔值分配给RRAM平铺网表的所有地网，布尔值1 被分配给RRAM平铺网表的所有电网。对于每个客户存储器验证RRAM平铺网表，其中k = 1,2，...。。。，N.

3. 发明授权

US07111264B2 Process and apparatus for fast assignment of objects to a rectangle 有权
标题翻译：将对象快速分配给矩形的过程和设备
公开(公告)号：US07111264B2
公开(公告)日：2006-09-19
申请号：US10688460
申请日：2003-10-17
申请人： Alexander E. Andreev , Andrey A. Nikitin , Ranko Scepanovic
发明人： Alexander E. Andreev , Andrey A. Nikitin , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Objects are assigned to points in a rectangle by dividing the rectangle is divided into a plurality of smaller rectangles and applying an object assignment procedure, such as Kuhn's algorithm, to initially assigned objects in each second rectangle. The initial assignment is performed by calculating a maximal cost of assignment of objects to points, and selecting an assignment of objects having a minimum value of maximal cost, identified by iteratively recalculating the maximal matching assignment based on a midpoint of between the minimum and maximum costs.
摘要翻译：通过将矩形划分为多个较小的矩形并将对象分配过程（例如Kuhn算法）应用于每个第二矩形中的初始分配对象，将对象分配给矩形中的点。通过计算对象到点的分配的最大成本并且选择具有最大成本的最小值的对象的分配来执行初始分配，通过基于最小和最大成本之间的中点迭代地重新计算最大匹配分配来识别。

4. 发明授权

US08006209B2 Method and system for outputting a sequence of commands and data described by a flowchart 有权
标题翻译：用于输出由流程图描述的命令和数据序列的方法和系统
公开(公告)号：US08006209B2
公开(公告)日：2011-08-23
申请号：US12315998
申请日：2008-12-09
申请人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
发明人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F8/66
摘要： The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A processor is generated to include the ROM, wherein the processor receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.
摘要翻译：本发明是用于输出由流程图描述的命令和数据序列的方法和系统。该方法包括以下步骤。接收描述命令和数据序列的流程图。流程图包括多个流程图符号。多个流程图符号中的每一个被分配有ROM（只读存储器）记录。分配的ROM记录存储在ROM中。产生处理器以包括ROM，其中处理器接收CLOCK信号作为输入，RESET信号，ENABLE信号和N个二进制输入x1，x2，...。。。 xN，并输出命令和数据的顺序。

5. 发明授权

US07415691B2 Method and system for outputting a sequence of commands and data described by a flowchart 失效
标题翻译：用于输出由流程图描述的命令和数据序列的方法和系统
公开(公告)号：US07415691B2
公开(公告)日：2008-08-19
申请号：US10894781
申请日：2004-07-20
申请人： Alexander E. Andreev , Andrey A. Nikitin , Ranko Scepanovic
发明人： Alexander E. Andreev , Andrey A. Nikitin , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. In an exemplary aspect of the present invention, a method for outputting a sequence of commands and data described by a flowchart includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A module (e.g., a CKD, or the like) is generated to include the ROM, wherein the module receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.
摘要翻译：本发明是用于输出由流程图描述的命令和数据序列的方法和系统。在本发明的一个示例性方面，用于输出由流程图描述的命令和数据序列的方法包括以下步骤。接收描述命令和数据序列的流程图。流程图包括多个流程图符号。多个流程图符号中的每一个被分配有ROM（只读存储器）记录。分配的ROM记录存储在ROM中。生成模块（例如，CKD等）以包括ROM，其中模块接收CLOCK信号，RESET信号，ENABLE信号和N个二进制输入x 1， x 2，...，。。并且输出命令和数据的序列。

6. 发明申请

US20090094571A1 Method and system for outputting a sequence of commands and data described by a flowchart 有权
标题翻译：用于输出由流程图描述的命令和数据序列的方法和系统
公开(公告)号：US20090094571A1
公开(公告)日：2009-04-09
申请号：US12315998
申请日：2008-12-09
申请人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
发明人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F8/66
摘要： The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A processor is generated to include the ROM, wherein the processor receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.
摘要翻译：本发明是用于输出由流程图描述的命令和数据序列的方法和系统。该方法包括以下步骤。接收描述命令和数据序列的流程图。流程图包括多个流程图符号。多个流程图符号中的每一个被分配有ROM（只读存储器）记录。分配的ROM记录存储在ROM中。产生处理器以包括ROM，其中处理器接收CLOCK信号作为输入，RESET信号，ENABLE信号和N个二进制输入x1，x2，...。。。 xN，并输出命令和数据的顺序。

7. 发明授权

US07168052B2 Yield driven memory placement system 有权
标题翻译：产量驱动记忆放置系统
公开(公告)号：US07168052B2
公开(公告)日：2007-01-23
申请号：US10875128
申请日：2004-06-23
申请人： Alexander E. Andreev , Andrey A. Nikitin , Ranko Scepanovic
发明人： Alexander E. Andreev , Andrey A. Nikitin , Ranko Scepanovic
IPC分类号： G06F17/50 , G06F9/45 , H03K17/693 , H03K19/00
CPC分类号： G06F17/5045 , G06F12/0292 , G06Q10/0875 , G06Q99/00
摘要： A user-defined memory design is mapped to memories of a base platform for an IC that contains a plurality of memory sets, each containing a plurality of memories of a predetermined type. An optimal memory set is selected from the plurality of memory sets for the design by selecting a preference rate for each memory set from the plurality of sets based on the design and its connections to portions of the IC, and selectively assigning the design to one of the memory sets based on the preference rate. The design is optimally mapped to a plurality of memories of the selected memory set by defining an index of the position of each customer memory in the selected memory set. The customer memories in the selected memory set are arranged in an order, and successive numbers of memories of the selected memory set are assigned to each customer memory in order.
摘要翻译：用户定义的存储器设计被映射到用于IC的基础平台的存储器，该存储器包含多个存储器组，每个存储器组包含预定类型的多个存储器。从设计的多个存储器集合中选择最佳存储器集合，其基于设计及其与IC的部分的连接，从多个集合中选择每个存储器组的偏好率，并且将该设计选择性地分配给基于优先级的内存集。通过定义所选择的存储器组中的每个顾客存储器的位置的索引，将设计最佳地映射到所选存储器组的多个存储器。所选择的存储器组中的客户存储器按顺序排列，并且所选择的存储器组的连续数量的存储器按顺序分配给每个客户存储器。

8. 发明授权

US07856577B2 Command language for memory testing 有权
标题翻译：内存测试的命令语言
公开(公告)号：US07856577B2
公开(公告)日：2010-12-21
申请号：US11944104
申请日：2007-11-21
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F11/00
CPC分类号： G06F11/27 , G06F8/41 , G11C29/16
摘要： A memory testing system for testing a plurality of memory locations in an electronic memory device is provided. The system includes a programmable memory device integrated into the electronic memory device capable of receiving and storing a compiled memory testing program. A processor is in communication with the programmable memory device to read and execute instructions from the compiled testing program stored in the programmable memory device and a command interpreter is configured to receive data from the processor related to commands to be executed during memory testing.
摘要翻译：提供了一种用于测试电子存储器件中的多个存储器位置的存储器测试系统。该系统包括集成到能够接收和存储编译的存储器测试程序的电子存储器件中的可编程存储器件。处理器与可编程存储器设备进行通信，以读取和执行存储在可编程存储器设备中的已编译测试程序的指令，并且命令解释器被配置为从存储器测试期间执行的命令接收来自处理器的数据。

9. 发明授权

US07231383B2 Search engine for large-width data 有权
标题翻译：大型数据搜索引擎
公开(公告)号：US07231383B2
公开(公告)日：2007-06-12
申请号：US10137874
申请日：2002-05-01
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F17/30 , G06F15/16
CPC分类号： G06F9/342 , Y10S707/99931 , Y10S707/99933 , Y10S707/99934
摘要： A search engine architecture substitutes short indices for large data widths, thereby reducing widths required for input to and output from the search engine. The search engine system comprises a search engine responsive to an input address to access an index in the search engine. The index has a width no greater than logarithm on base 2 of the search engine capacity, thereby permitting the search engine to be embodied in an IC chip of reduced area. A driver responds to input commands and to the search engine status to manage indices in the search engine and enable the memory to access its addressable locations based on indices in the search engine.
摘要翻译：搜索引擎架构将短索引替换为大数据宽度，从而减少输入到搜索引擎输出所需的宽度。搜索引擎系统包括响应于输入地址以访问搜索引擎中的索引的搜索引擎。该索引具有不大于搜索引擎容量的基础2上的对数的宽度，从而允许搜索引擎体现在缩小区域的IC芯片中。驱动程序响应输入命令和搜索引擎状态来管理搜索引擎中的索引，并使内存能够基于搜索引擎中的索引访问其可寻址位置。

10. 发明授权

US07050582B1 Pseudo-random one-to-one circuit synthesis 有权
标题翻译：伪随机一对一电路合成
公开(公告)号：US07050582B1
公开(公告)日：2006-05-23
申请号：US09883733
申请日：2001-06-18
申请人： Alexander E. Andreev , Igor A. Vikhliantsev , Ranko Scepanovic
发明人： Alexander E. Andreev , Igor A. Vikhliantsev , Ranko Scepanovic
IPC分类号： H04K1/00 , H04L9/00
CPC分类号： H04L9/0668
摘要： A method of defining a transformation between an input signal and an output signal. The transformation may implement a pseudo-random one-to-one function that may be implemented in hardware and/or software or modeled in software. The method may comprise the steps of (A) allocating the input signal among a plurality of block input signals, (B) establishing a plurality of transfer functions where each transfer function may be configured to present a plurality of unique symbols as a block output signal responsive to said block input signal, and (C) concatenating the block output signals to form the output signal.
摘要翻译：一种定义输入信号和输出信号之间变换的方法。该转换可以实现可以在硬件和/或软件中实现或以软件建模的伪随机一对一功能。该方法可以包括以下步骤：（A）在多个块输入信号之间分配输入信号，（B）建立多个传递函数，其中每个传递函数可被配置为呈现多个唯一符号作为块输出信号响应于所述块输入信号，以及（C）串联块输出信号以形成输出信号。

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