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1. 发明授权

US08077623B2 Signal routing in processor arrays 有权
标题翻译：处理器阵列中的信号路由
公开(公告)号：US08077623B2
公开(公告)日：2011-12-13
申请号：US12367814
申请日：2009-02-09
申请人： Andrew William George Duller , William Philip Robbins
发明人： Andrew William George Duller , William Philip Robbins
IPC分类号： G01R31/08
CPC分类号： G06F15/17375
摘要： There is provided a method for routing a plurality of signals in a processor array, the processor array comprising a plurality of processor elements interconnected by a network of switches, each signal having a respective source processor element and at least one destination processor element in the processor array, the method comprising (i) identifying a signal from the plurality of unrouted signals to route; (ii) identifying a candidate route from the source processor element to the destination processor element, the candidate route using a first plurality of switches; (iii) evaluating the candidate route by determining whether there are offset values that allow the signal to be routed through the first plurality of switches; and (iv) attempting to route the signal using one of the offset values identified in step (iii).
摘要翻译：提供了一种用于在处理器阵列中路由多个信号的方法，所述处理器阵列包括通过交换机网络互连的多个处理器元件，每个信号具有相应的源处理器元件和处理器中的至少一个目的地处理器元件阵列，所述方法包括（i）识别来自所述多个未路由信号的信号以路由; （ii）识别从所述源处理器元件到所述目的地处理器元件的候选路线，所述候选路线使用第一多个开关; （iii）通过确定是否存在允许信号通过第一多个交换机路由的偏移值来评估候选路线; 以及（iv）使用步骤（iii）中识别的偏移值之一尝试路由信号。

2. 发明授权

US5805914A Data pipeline system and data encoding method 失效
公开(公告)号：US5805914A
公开(公告)日：1998-09-08
申请号：US479279
申请日：1995-06-07
申请人： Adrian Philip Wise , Martin William Sotheran , William Philip Robbins , Anthony Peter John Claydon , Kevin James Boyd , Helen Rosemary Finch
发明人： Adrian Philip Wise , Martin William Sotheran , William Philip Robbins , Anthony Peter John Claydon , Kevin James Boyd , Helen Rosemary Finch
IPC分类号： G06F13/38 , G06F15/00
CPC分类号： G06F13/38 , G06F15/00
摘要： A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

3. 发明授权

US5809270A Inverse quantizer 失效
标题翻译：逆量化器
公开(公告)号：US5809270A
公开(公告)日：1998-09-15
申请号：US947727
申请日：1997-09-25
申请人： William Philip Robbins
发明人： William Philip Robbins
IPC分类号： G06F9/38 , G06F9/44 , G06F12/02 , G06F12/04 , G06F12/06 , G06F13/16 , G06F13/28 , G06T9/00 , H04N7/26 , H04N7/50 , G06F9/30
CPC分类号： G06F9/4436 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/16 , G06F13/28 , G06F9/3867 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/13 , H04N19/91
摘要： A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.
摘要翻译：多标准视频解压缩装置具有通过布置为流水线处理机的两线接口互连的多个级。控制令牌和数据令牌通过单个双线接口，以承载格式携带控制和数据。令牌解码电路位于某些阶段，用于将某些令牌识别为与该级相关的控制令牌，并沿着管道传递未被识别的控制令牌。重新配置处理电路定位在选定的阶段，并且响应于识别的控制令牌，以重新配置这样的阶段来处理所识别的数据令牌。公开了各种独特的支持子系统电路和处理技术来实现该系统。

4. 发明授权

US5761741A Technique for addressing a partial word and concurrently providing a substitution field 失效
标题翻译：解决部分词并同时提供替代字段的技术
公开(公告)号：US5761741A
公开(公告)日：1998-06-02
申请号：US473868
申请日：1995-06-07
申请人： William Philip Robbins , Adrian Philip Wise
发明人： William Philip Robbins , Adrian Philip Wise
IPC分类号： G06F12/02 , G06F12/04
CPC分类号： G06F12/04
摘要： A method and apparatus for addressing memory is disclosed. In one embodiment, a procedure for providing a word with fixed width, having a fixed number of bits to be used for addressing variable width data, and having a width defining field and address field, is disclosed. In addition, a procedure for addressing memory with a fixed width word, having a fixed number of bits, to be used for addressing data and having a substitution field and an address field, is discussed. Also, an apparatus for addressing memory, including a state machine and an arithmetic core is disclosed.
摘要翻译：公开了一种用于寻址存储器的方法和装置。在一个实施例中，公开了一种用于提供具有固定宽度的字，具有用于寻址可变宽度数据的固定数量的位以及具有定义字段和地址字段的宽度的一个过程。另外，讨论了用于寻址用于寻址数据并具有替换字段和地址字段的具有固定位数的固定宽度字的存储器的过程。另外，公开了一种用于寻址存储器的设备，包括状态机和运算核心。

5. 发明授权

US5699544A Method and apparatus for using a fixed width word for addressing variable width data 失效
标题翻译：使用固定宽度字寻址可变宽度数据的方法和装置
公开(公告)号：US5699544A
公开(公告)日：1997-12-16
申请号：US474220
申请日：1995-06-07
申请人： William Philip Robbins , Adrian Philip Wise
发明人： William Philip Robbins , Adrian Philip Wise
IPC分类号： G06F12/04
CPC分类号： G06F12/04
摘要： A method for addressing memory uses a word with a fixed width, having a fixed number of bits, and having a width defining field and address field. The procedure is adapted to addressing variable width data. In one embodiment memory can be addressed using a fixed width word having a fixed number of bits, and having both a substitution field and an address field.
摘要翻译：寻址存储器的方法使用具有固定宽度的固定宽度的字，并且具有定义字段和地址字段的宽度。该过程适用于寻址可变宽度数据。在一个实施例中，可以使用具有固定位数的固定宽度字来寻址存储器，并且具有替代字段和地址字段。

6. 发明授权

US07987340B2 Communications in a processor array 有权
标题翻译：处理器阵列中的通信
公开(公告)号：US07987340B2
公开(公告)日：2011-07-26
申请号：US10546616
申请日：2004-02-19
申请人： Gajinder Panesar , Anthony Peter John Claydon , William Philip Robbins , Alex Orr , Andrew Duller
发明人： Gajinder Panesar , Anthony Peter John Claydon , William Philip Robbins , Alex Orr , Andrew Duller
IPC分类号： G06F15/80
CPC分类号： G06F13/4286
摘要： Data is transmitted from a sending processor over a network to one or more receiving processor in a forward direction during an allocated slot, and acknowledge signals are sent in a reverse direction during the same allocated slot, to indicate whether the receiving processor is able to receive data If one or more of the receiving processors indicates that it is unable to receive the data, the data is retransmitted during the next allocated slot. This means that the sending processor is able to determine within the slot period whether a retransmission is necessary, but that the slot period only needs to be long enough for one-way communication.
摘要翻译：在所分配的时隙期间，数据从发送处理器通过网络传送到一个或多个接收处理器，并且在相同的分配时隙期间以相反的方向发送确认信号，以指示接收处理器是否能够接收数据如果一个或多个接收处理器指示它不能接收数据，则在下一个分配的时隙期间重传该数据。这意味着发送处理器能够在时隙周期内确定是否需要重传，但是时隙周期只需要足够长以进行单向通信。

7. 发明授权

US6122726A Data pipeline system and data encoding method 失效
标题翻译：数据流水线系统和数据编码方法
公开(公告)号：US6122726A
公开(公告)日：2000-09-19
申请号：US984546
申请日：1997-12-03
申请人： Adrian Philip Wise , William Philip Robbins , Martin William Sotheran
发明人： Adrian Philip Wise , William Philip Robbins , Martin William Sotheran
IPC分类号： G06F9/38 , G06F9/44 , G06F15/00 , G06F15/16 , G06F15/80 , G06F15/82 , H04L23/00 , H04N7/26 , H04N7/50
CPC分类号： G06F9/3871 , G06F9/3873 , G06F9/4436 , H04N19/42 , H04N19/61 , H04N19/13 , H04N19/91
摘要： A pipeline structure processes data in a series of stages, each of which has a data input latch (LDIN) and passes it on to the next stage in the pipeline via a data output latch (LDOUT). The stages are preferably connected to two non-overlapping clock phases (PH0, PH1) Adjacent stages are also connected via a validation line (IN.sub.-- VALID, OUT.sub.-- VALID) and an acceptance line (IN.sub.-- ACCEPT, OUT.sub.-- ACCEPT), and in some embodiments also via an extension bit line (IN.sub.-- EXTN, OUT.sub.-- EXTN). Input data is transferred from any stage to the following device on every complete period of both clock signals only if both the validation and acceptance signals in the respective latch are in an affirmative state, whereby data is transferred between stages regardless of the state of the validation and acceptance signals in other stages. A two-wire interface is thus formed between the stages. Address decoding circuitry may also be included in any of the stages so that a stage manipulates the input data stream only when one or more current data words have a predetermined bit pattern. The extension bit line conveys an extension bit that separates fields of different data blocks in the data stream. The invention also includes a method for uniquely encoding data blocks so that only intended pipeline stages are activated, with others simply passing input data through.
摘要翻译：流水线结构处理一系列级数据，每一级具有数据输入锁存器（LDIN），并通过数据输出锁存器（LDOUT）将其传送到流水线中的下一级。这些级优选地连接到两个非重叠时钟相位（PH0，PH1）。相邻级还经由验证线（IN-VALID，OUT-VALID）和接受线（IN-ACCEPT，OUT-ACCEPT）连接，以及在一些实施例中也通过扩展位线（IN-EXTN，OUT-EXTN）。只有当相应锁存器中的验证和接收信号都处于肯定状态时，输入数据才能从两个时钟信号的每个完整周期从任何阶段传输到下一个设备，从而数据在阶段之间传输，而不管验证状态如何和其他阶段的验收信号。因此，在两个级之间形成两线接口。地址解码电路也可以包括在任何一个阶段中，使得仅当一个或多个当前数据字具有预定位模式时，才操纵输入数据流。扩展位线传送分割数据流中不同数据块的字段的扩展位。本发明还包括一种用于唯一地编码数据块的方法，使得仅预期的流水线级被激活，其他简单地传递输入数据。

8. 发明授权

US6035126A Data pipeline system and data encoding method 失效
公开(公告)号：US6035126A
公开(公告)日：2000-03-07
申请号：US483020
申请日：1995-06-07
申请人： Adrian Philip Wise , Martin William Sotheran , William Philip Robbins
发明人： Adrian Philip Wise , Martin William Sotheran , William Philip Robbins
IPC分类号： G06F7/00 , G06F9/38 , G06F9/44 , G06F12/02 , G06F12/04 , G06F12/06 , G06F13/16 , G06F13/28 , G06T9/00 , H04N7/26 , H04N7/50 , G06F15/00
CPC分类号： G06F9/3867 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/16 , G06F13/1673 , G06F13/1689 , G06F13/28 , G06F9/4436 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/13 , H04N19/91
摘要： A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

9. 发明授权

US5835740A Data pipeline system and data encoding method 失效
公开(公告)号：US5835740A
公开(公告)日：1998-11-10
申请号：US487224
申请日：1995-06-07
申请人： Adrian Philip Wise , Martin William Sotheran , William Philip Robbins
发明人： Adrian Philip Wise , Martin William Sotheran , William Philip Robbins
IPC分类号： G06F9/00 , G06F9/38 , G06F9/44 , G06F12/02 , G06F12/04 , G06F12/06 , G06F13/16 , G06F13/28 , G06F13/38 , G06F15/00 , H04N7/26 , H04N7/50
CPC分类号： G06F9/3867 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/16 , G06F13/28 , G06F9/4436 , H04N19/42 , H04N19/423 , H04N19/44 , H04N19/61 , H04N19/13 , H04N19/91
摘要： A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

10. 发明授权

US06799246B1 Memory interface for reading/writing data from/to a memory 失效
标题翻译：用于从/向存储器读取/写入数据的存储器接口
公开(公告)号：US06799246B1
公开(公告)日：2004-09-28
申请号：US08991234
申请日：1997-12-16
申请人： Adrian P. Wise , Kevin Douglas Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter J. Claydon , Donald W. Walker Patterson , Mark Barnes , Andrew Peter Kuligowski , William Philip Robbins , Nicholas Birch , David Andrew Barnes
发明人： Adrian P. Wise , Kevin Douglas Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter J. Claydon , Donald W. Walker Patterson , Mark Barnes , Andrew Peter Kuligowski , William Philip Robbins , Nicholas Birch , David Andrew Barnes
IPC分类号： G06F1208
CPC分类号： H04N21/4307 , G06F12/0207 , G06F12/04 , G06F13/16 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91 , H04N21/4305 , H04N21/44004
摘要： A memory interface for connecting a bus to memory comprises an input, a buffer, an address input, a generator, and a writer. The input receives a plurality of data words from the bus. The buffer buffers the data words received from the bus. The address input receives from the bus addresses associated with the plurality of data words. The generator generates a series of addresses in the memory into which the buffered data words may be written. The series of addresses are derived from the received addresses. The writer writes the buffered data words into the memory at the generated addresses.
摘要翻译：用于将总线连接到存储器的存储器接口包括输入，缓冲器，地址输入，发生器和写入器。输入从总线接收多个数据字。缓冲器缓冲从总线接收的数据字。地址输入从与多个数据字相关联的总线地址接收。发生器在存储器中产生一系列可以写入缓冲数据字的地址。该地址系列从接收到的地址中导出。写入器将生成的地址将缓冲的数据字写入存储器。

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