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1. 发明授权

US07987340B2 Communications in a processor array 有权
标题翻译：处理器阵列中的通信
公开(公告)号：US07987340B2
公开(公告)日：2011-07-26
申请号：US10546616
申请日：2004-02-19
申请人： Gajinder Panesar , Anthony Peter John Claydon , William Philip Robbins , Alex Orr , Andrew Duller
发明人： Gajinder Panesar , Anthony Peter John Claydon , William Philip Robbins , Alex Orr , Andrew Duller
IPC分类号： G06F15/80
CPC分类号： G06F13/4286
摘要： Data is transmitted from a sending processor over a network to one or more receiving processor in a forward direction during an allocated slot, and acknowledge signals are sent in a reverse direction during the same allocated slot, to indicate whether the receiving processor is able to receive data If one or more of the receiving processors indicates that it is unable to receive the data, the data is retransmitted during the next allocated slot. This means that the sending processor is able to determine within the slot period whether a retransmission is necessary, but that the slot period only needs to be long enough for one-way communication.
摘要翻译：在所分配的时隙期间，数据从发送处理器通过网络传送到一个或多个接收处理器，并且在相同的分配时隙期间以相反的方向发送确认信号，以指示接收处理器是否能够接收数据如果一个或多个接收处理器指示它不能接收数据，则在下一个分配的时隙期间重传该数据。这意味着发送处理器能够在时隙周期内确定是否需要重传，但是时隙周期只需要足够长以进行单向通信。

2. 发明授权

US5805914A Data pipeline system and data encoding method 失效
公开(公告)号：US5805914A
公开(公告)日：1998-09-08
申请号：US479279
申请日：1995-06-07
申请人： Adrian Philip Wise , Martin William Sotheran , William Philip Robbins , Anthony Peter John Claydon , Kevin James Boyd , Helen Rosemary Finch
发明人： Adrian Philip Wise , Martin William Sotheran , William Philip Robbins , Anthony Peter John Claydon , Kevin James Boyd , Helen Rosemary Finch
IPC分类号： G06F13/38 , G06F15/00
CPC分类号： G06F13/38 , G06F15/00
摘要： A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

3. 发明授权

US6154871A Error detection and correction system for a stream of encoded data 失效
标题翻译：用于编码数据流的错误检测和校正系统
公开(公告)号：US6154871A
公开(公告)日：2000-11-28
申请号：US971198
申请日：1997-11-14
申请人： Anthony Peter John Claydon , Richard John Gammack , William Philip Robbins , Charles Dunlop MacFarlane , Thomas Foxcroft , Andrew Peter Kuligowski , Richard James Thomas
发明人： Anthony Peter John Claydon , Richard John Gammack , William Philip Robbins , Charles Dunlop MacFarlane , Thomas Foxcroft , Andrew Peter Kuligowski , Richard James Thomas
IPC分类号： H03M13/00 , H03M13/23 , H03M13/41 , H04L1/00
CPC分类号： H04L1/0071 , H03M13/1515 , H03M13/23 , H03M13/2936 , H03M13/3961 , H03M13/41 , H03M13/4107 , H03M13/4169 , H03M13/6325 , H03M13/6362 , H03M13/6502 , H03M13/6516 , H04L1/0009 , H04L1/0054 , H04L1/0059 , H04L1/0065 , H04L1/0068
摘要： The invention provides a decoder of symbols of received data, the data being encoded according to a convolutional encoding scheme and transmitted through a communications channel. The data is punctuated according to a puncturing matrix, and has a plurality of state values which describe a sequence of state transitions. The decoder has a generation unit that accepts the received data for calculating metrics of the transitions thereof. A selector responsive to the generation unit selects a path of transitions corresponding to the path produced by a transmitter of the data stream. A traceback unit maintains historical information representative of sequential decision operations of the selector. A counter is provided for counting illegal state transitions of the path selected by the selector, and a control unit, responsive to the counter, determines a puncture rate and adjusts a puncture phase of the received data. The decoder can be used in a VLSI receiver circuit which is adapted to the reception of QPSK modulated data.
摘要翻译：本发明提供了一种接收数据符号的解码器，该数据根据卷积编码方案进行编码，并通过通信信道传输。根据打孔矩阵对数据进行标点，并且具有描述状态转换序列的多个状态值。解码器具有接收用于计算其转换的度量的接收数据的生成单元。响应于生成单元的选择器选择与由数据流的发送器产生的路径相对应的转换路径。追溯单元维护表示选择器的顺序决定操作的历史信息。提供一个计数器，用于计数由选择器选择的路径的非法状态转换，并且响应于计数器的控制单元确定穿刺率并调整接收数据的穿孔阶段。解码器可以用于适合于接收QPSK调制数据的VLSI接收机电路中。

4. 发明授权

US5742622A Error detection and correction system for a stream of encoded data 失效
公开(公告)号：US5742622A
公开(公告)日：1998-04-21
申请号：US638273
申请日：1996-04-26
申请人： Anthony Peter John Claydon , Richard John Gammack , William Philip Robbins , Charles Dunlop MacFarlane , Thomas Foxcroft , Andrew Peter Kuligowski , Richard James Thomas
发明人： Anthony Peter John Claydon , Richard John Gammack , William Philip Robbins , Charles Dunlop MacFarlane , Thomas Foxcroft , Andrew Peter Kuligowski , Richard James Thomas
IPC分类号： H03M13/00 , H03M13/23 , H03M13/41 , H04L1/00 , H03M13/12
CPC分类号： H04L1/0071 , H03M13/1515 , H03M13/23 , H03M13/2936 , H03M13/3961 , H03M13/41 , H03M13/4107 , H03M13/4169 , H03M13/6325 , H03M13/6362 , H03M13/6502 , H03M13/6516 , H04L1/0009 , H04L1/0054 , H04L1/0059 , H04L1/0065 , H04L1/0068
摘要： The invention provides a decoder of symbols of received data, the data being encoded according to a convolutional encoding scheme and transmitted through a communications channel. The data is punctuated according to a puncturing matrix, and has a plurality of state values which describe a sequence of state transitions. The decoder has a generation unit that accepts the received data for calculating metrics of the transitions thereof. A selector responsive to the generation unit selects a path of transitions corresponding to the path produced by a transmitter of the data stream. A traceback unit maintains historical information representative of sequential decision operations of the selector. A counter is provided for counting illegal state transitions of the path selected by the selector, and a control unit, responsive to the counter, determines a puncture rate and adjusts a puncture phase of the received data. The decoder can be used in a VLSI receiver circuit which is adapted to the reception of QPSK modulated data.

5. 发明授权

US5835792A Token-based adaptive video processing arrangement 失效
公开(公告)号：US5835792A
公开(公告)日：1998-11-10
申请号：US487134
申请日：1995-06-07
申请人： Adrian P. Wise , Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , Mark Barnes , Andrew Peter Kuligowski , William P. Robbins , Nicholas Birch , David Andrew Barnes
发明人： Adrian P. Wise , Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , Mark Barnes , Andrew Peter Kuligowski , William P. Robbins , Nicholas Birch , David Andrew Barnes
IPC分类号： H04N5/92 , G06F3/14 , G06F12/00 , G06F12/02 , G06F12/04 , G06F12/06 , G06F12/08 , G06F13/00 , G06F13/16 , G06F13/28 , G06F13/37 , G06T9/00 , G11B7/00 , G11B27/10 , H03M7/30 , H03M7/40 , H03M7/42 , H04L7/00 , H04L7/08 , H04L12/433 , H04N7/26 , H04N7/32 , H04N7/50 , H04N7/52
CPC分类号： H04N21/4307 , G06F12/0207 , G06F13/16 , G06F13/28 , H04N19/42 , H04N19/423 , H04N19/61 , H04N21/4305 , H04N21/44004 , G06F12/04 , H04N19/13 , H04N19/91
摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

6. 发明授权

US5829007A Technique for implementing a swing buffer in a memory array 失效
标题翻译：在存储器阵列中实现摆动缓冲器的技术
公开(公告)号：US5829007A
公开(公告)日：1998-10-27
申请号：US486908
申请日：1995-06-07
申请人： Adrian P. Wise , Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , Mark Barnes , Andrew Peter Kuligowski , William P. Robbins , Nicholas Birch , David Andrew Barnes
发明人： Adrian P. Wise , Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , Mark Barnes , Andrew Peter Kuligowski , William P. Robbins , Nicholas Birch , David Andrew Barnes
IPC分类号： H04N5/92 , G06F3/14 , G06F12/00 , G06F12/02 , G06F12/04 , G06F12/06 , G06F12/08 , G06F13/00 , G06F13/16 , G06F13/28 , G06F13/37 , G06T9/00 , G11B7/00 , G11B27/10 , H03M7/30 , H03M7/40 , H03M7/42 , H04L7/00 , H04L7/08 , H04L12/433 , H04N7/26 , H04N7/32 , H04N7/50 , H04N7/52
CPC分类号： H04N21/4307 , G06F12/0207 , G06F13/16 , G06F13/28 , H04N19/42 , H04N19/423 , H04N19/61 , H04N21/4305 , H04N21/44004 , G06F12/04 , H04N19/13 , H04N19/91
摘要： A RAM implementation of asynchronous swing buffering is provided in which two buffers are operated asynchronously; one is written while the other is read. Accordingly, this allows for a data stream having a fast rate of through-put to be resynchronized to another rate, while still maintaining a desired rate. In the invention, the write control and read control both have state indicators for communicating which buffer they are using and whether the controls are waiting for access or are, in fact, accessing that buffer.
摘要翻译：提供了异步摆动缓冲的RAM实现，其中两个缓冲器是异步操作的; 一个是写在另一个被读取。因此，这允许具有快速吞吐速率的数据流与另一个速率重新同步，同时仍然保持期望的速率。在本发明中，写入控制和读取控制都具有用于通信它们正在使用哪个缓冲器的状态指示符，以及控制是否正在等待访问，或实际上访问该缓冲器。

7. 发明授权

US07549081B2 Processor array 有权
标题翻译：处理器阵列
公开(公告)号：US07549081B2
公开(公告)日：2009-06-16
申请号：US10521889
申请日：2003-06-27
申请人： William Robbins , Michael Davison , Simon Howell , Anthony Peter John Claydon
发明人： William Robbins , Michael Davison , Simon Howell , Anthony Peter John Claydon
IPC分类号： G06F11/00
CPC分类号： G06F11/2051 , G06F11/2038 , G06F11/2041
摘要： An array of processing elements can incorporate a degree of redundancy. Specifically, the array includes one or more spare, or redundant, rows of array elements, in addition to the number required to implement the intended function or functions of the device. If a defect occurs in one of the processors in the device, then the entire row which includes that defective processor is not used, and is replaced by a spare row.
摘要翻译：一系列处理元件可以并入一定程度的冗余。具体而言，除了实现设备的预期功能或功能所需的数量之外，该阵列还包括一个或多个备用或冗余的数组元素行。如果设备中的一个处理器中出现缺陷，则不使用包含该缺陷处理器的整个行，并由备用行替换。

8. 发明授权

US5984512A Method for storing video information 失效
标题翻译：存储视频信息的方法
公开(公告)号：US5984512A
公开(公告)日：1999-11-16
申请号：US488348
申请日：1995-06-07
申请人： Anthony Mark Jones , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , William P. Robbins , Nicholas Birch , David Andrew Barnes
发明人： Anthony Mark Jones , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , William P. Robbins , Nicholas Birch , David Andrew Barnes
IPC分类号： H04N5/92 , G06F3/14 , G06F12/00 , G06F12/02 , G06F12/04 , G06F12/06 , G06F12/08 , G06F13/00 , G06F13/16 , G06F13/28 , G06F13/37 , G06T9/00 , G11B7/00 , G11B27/10 , H03M7/30 , H03M7/40 , H03M7/42 , H04L7/00 , H04L7/08 , H04L12/433 , H04N7/26 , H04N7/32 , H04N7/50 , H04N7/52 , G06F17/00
CPC分类号： H04N21/4307 , G06F12/0207 , G06F13/16 , G06F13/28 , H04N19/42 , H04N19/423 , H04N19/61 , H04N21/4305 , H04N21/44004 , G06F12/04 , H04N19/13 , H04N19/91
摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in select stages and are responsive to a recognized control token for reconfiguring such stages to handle an identified DATA Token. A wide variety of unique supporting subsystems circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.
摘要翻译：一种MPEG视频解压缩方法和装置，利用被布置为流水线处理机的两线接口互连的多个级。控制令牌和数据令牌通过单个双线接口，用于携带控制和令牌格式。令牌解码电路位于某些阶段，用于将某些令牌识别为与该级相关的控制令牌，并沿着管道传递未被识别的控制令牌。重新配置处理电路位于选择阶段，并响应于识别的控制令牌，以重新配置这些阶段来处理所识别的数据令牌。公开了各种独特的支持子系统电路和处理技术，用于实现系统，包括存储器寻址，使用公共处理块变换数据，时间同步，异步摆动缓冲，存储视频信息，并行霍夫曼解码器等。

9. 发明授权

US07996652B2 Processor architecture with switch matrices for transferring data along buses 有权
标题翻译：具有用于沿着总线传输数据的开关矩阵的处理器架构
公开(公告)号：US07996652B2
公开(公告)日：2011-08-09
申请号：US12070790
申请日：2008-02-21
申请人： Anthony Peter John Claydon , Anne Patricia Claydon
发明人： Anthony Peter John Claydon , Anne Patricia Claydon
IPC分类号： G06F9/00
CPC分类号： G06F15/8023
摘要： A processor architecture includes a plurality of elements arranged in an array of rows and columns and a plurality of first and second bus pairs with the first pair being located between different adjacent rows of the array and having first and second buses running in opposite directions and the second bus pair being located between different adjacent columns of the array and having third and fourth buses running in opposite directions and intersecting the first and second buses. A plurality of switch matrices located at an intersection of one of the first bus pairs and one of the second bus pairs includes inputs and outputs for first, second, third and fourth buses and switch elements for switchably connecting the inputs and outputs.
摘要翻译：处理器架构包括布置成行和列阵列的多个元件以及多个第一和第二总线对，其中第一对位于阵列的不同相邻行之间并且具有沿相反方向运行的第一和第二总线，第二总线对位于阵列的不同相邻列之间，并且具有以相反方向运行并与第一和第二总线相交的第三和第四总线。位于第一总线对和第二总线对之一的交叉点处的多个开关矩阵包括用于第一，第二，第三和第四总线的输入和输出以及用于可切换地连接输入和输出的开关元件。

10. 发明申请

US20080222339A1 Processor architecture with switch matrices for transferring data along buses 有权
标题翻译：具有用于沿着总线传输数据的开关矩阵的处理器架构
公开(公告)号：US20080222339A1
公开(公告)日：2008-09-11
申请号：US12070790
申请日：2008-02-21
申请人： Anthony Peter John Claydon , Anne Patricia Claydon
发明人： Anthony Peter John Claydon , Anne Patricia Claydon
IPC分类号： G06F13/36
CPC分类号： G06F15/8023
摘要： There is described a processor architecture, comprising: a plurality of first bus pairs, each first bus pair including a respective first bus running in a first direction (for example, left to right) and a respective second bus running in a second direction opposite to the first direction (for example right to left); a plurality of second bus pairs, each second bus pair including a respective third bus running in a third direction (for example downwards) and a respective fourth bus running in a fourth direction opposite to the third direction (for example upwards), the third and fourth buses intersecting the first and second buses; a plurality of switch matrices, each switch matrix located at an intersection of a first and a second pair of buses; a plurality of elements arranged in an array, each element being arranged to receive data from a respective first or second bus, and transfer data to a respective first or second bus. The elements in the array include processing elements, for operating on received data, and memory elements, for storing received data. The described architecture has the advantage that it requires relatively little memory, and the memory requirements can be met by local memory elements in the array.
摘要翻译：描述了一种处理器架构，包括：多个第一总线对，每个第一总线对包括在第一方向（例如从左到右）上运行的相应的第一总线，以及以与第二总线相对的第二方向运行的相应的第二总线第一个方向（例如从右到左）; 多个第二总线对，每个第二总线对包括沿第三方向（例如向下）行进的相应的第三总线和沿与第三方向（例如向上）相反的第四方向行进的相应的第四总线，第三总线和第四辆巴士与第一和第二辆公交车相交; 多个开关矩阵，每个开关矩阵位于第一和第二对总线的交点处; 以阵列布置的多个元件，每个元件被布置成从相应的第一或第二总线接收数据，并将数据传送到相应的第一或第二总线。阵列中的元素包括用于对接收到的数据进行操作的处理元件和用于存储接收数据的存储器元件。所描述的架构的优点在于它需要相对较少的存储器，并且存储器要求可以由阵列中的本地存储器元件来满足。

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