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1. 发明申请

US20100025364A1 Method for Manufacturing Multiple Layers of Waveguides 有权
标题翻译：制造多层波导的方法
公开(公告)号：US20100025364A1
公开(公告)日：2010-02-04
申请号：US12517692
申请日：2008-08-29
申请人： Andrew T.S. Pomerene , Timothy J. Conway , Craig M. Hill , Mark Jaso
发明人： Andrew T.S. Pomerene , Timothy J. Conway , Craig M. Hill , Mark Jaso
IPC分类号： B29D11/00
CPC分类号： G02B6/12002 , B82Y20/00 , G02B6/1223 , G02B6/132 , G02B6/136
摘要： A method for manufacturing multiple layers of waveguides is disclosed. Initially, a first cladding layer is deposited on a substrate, a first inner cladding layer is then deposited on the first cladding layer, and a first waveguide material is deposited on the first inner cladding layer. The first inner cladding layer and the first waveguide material are then selectively etched to form a first waveguide layer. Next, a second inner cladding layer followed by a second cladding layer are deposited on the first waveguide layer. The second inner cladding layer and the second cladding layer are removed by using a chemical-mechanical polishing process selective to the first waveguide material. A third inner cladding layer followed by a second waveguide material are deposited on the first waveguide material. The third inner cladding layer and the second waveguide material are then selectively etched to form a second waveguide layer. Finally, a fourth inner cladding layer followed by a third cladding layer are deposited on the second waveguide layer.
摘要翻译：公开了制造多层波导的方法。首先，在基板上沉积第一包层，然后在第一包层上沉积第一内包层，在第一内包层上沉积第一波导材料。然后选择性地蚀刻第一内包层和第一波导材料以形成第一波导层。接下来，在第一波导层上沉积第二内包层和第二覆层。通过使用对第一波导材料选择性的化学机械抛光工艺来除去第二内包层和第二包覆层。在第一波导材料上沉积第三内包层和第二波导材料。然后选择性地蚀刻第三内包层和第二波导材料以形成第二波导层。最后，在第二波导层上沉积第四内包层和第三覆层。

2. 发明申请

US20100092682A1 Method for Fabricating a Heater Capable of Adjusting Refractive Index of an Optical Waveguide 审中-公开
$Method for Fabricating a Heater Capable of Adjusting Refractive Index of an Optical Waveguide$
标题翻译：制造能够调整光波导折射率的加热器的方法
公开(公告)号：US20100092682A1
公开(公告)日：2010-04-15
申请号：US12521855
申请日：2008-08-29
申请人： Daniel N. Carothers , Craig M. Hill , Andrew T.S. Pomerene , Thomas J. McIntyre , Timothy J. Conway , Jonathan N. Ishii
发明人： Daniel N. Carothers , Craig M. Hill , Andrew T.S. Pomerene , Thomas J. McIntyre , Timothy J. Conway , Jonathan N. Ishii
IPC分类号： B05D3/02
CPC分类号： G02B6/10 , G02B6/12033 , G02F1/011 , G02F1/0147
摘要： A method for fabricating a thermal optical heating element capable of adjusting refractive index of an optical waveguide is disclosed. A silicon block is initially formed on a cladding layer on a silicon substrate. The silicon block is located in close proximity to an optical waveguide. A cobalt layer is deposited on the silicon block. The silicon block is then annealed to cause the cobalt layer to react with the silicon block to form a cobalt silicide layer. The silicon block is again annealed to cause the cobalt silicide layer to transform into a cobalt di-silicide layer.
摘要翻译：公开了一种制造能够调节光波导的折射率的热光学加热元件的方法。最初在硅衬底上的包覆层上形成硅块。硅块位于靠近光波导的位置。钴层沉积在硅块上。然后将硅块退火以使钴层与硅块反应形成硅化钴层。再次退火硅块以使硅化钴层转变成二硅化钴层。

3. 发明申请

US20090111200A1 Method for Fabricating Electronic and Photonic Devices on a Semiconductor Substrate 有权
标题翻译：在半导体基板上制造电子和光子器件的方法
公开(公告)号：US20090111200A1
公开(公告)日：2009-04-30
申请号：US12201943
申请日：2008-08-29
申请人： Daniel N. Carothers , Craig M. Hill , Andrew T.S. Pomerene , Timothy J. Conway , Rick L. Thompson , Vu A. Vu , Robert Kamocsai , Joe Giunta , Jonathan N. Ishii
发明人： Daniel N. Carothers , Craig M. Hill , Andrew T.S. Pomerene , Timothy J. Conway , Rick L. Thompson , Vu A. Vu , Robert Kamocsai , Joe Giunta , Jonathan N. Ishii
IPC分类号： H01L21/02
CPC分类号： H01L27/0617
摘要： A method for fabricating photonic and electronic devices on a substrate is disclosed. Multiple slabs are initially patterned and etched on a layer of a substrate. An electronic device is fabricated on a first one of the slabs and a photonic device is fabricated on a second one of the slabs, such that the electronic device and the photonic device are formed on the same layer of the substrate.
摘要翻译：公开了一种在衬底上制造光子和电子器件的方法。最初对多个板坯进行图案化并在衬底层上进行蚀刻。在第一板上制造电子器件，并且在第二板上制造光子器件，使得电子器件和光子器件形成在基片的同一层上。

4. 发明授权

US08192638B2 Method for manufacturing multiple layers of waveguides 有权
标题翻译：制造多层波导的方法
公开(公告)号：US08192638B2
公开(公告)日：2012-06-05
申请号：US12517692
申请日：2008-08-29
申请人： Andrew T. S. Pomerene , Timothy J. Conway , Craig M. Hill , Mark Jaso
发明人： Andrew T. S. Pomerene , Timothy J. Conway , Craig M. Hill , Mark Jaso
IPC分类号： B29D11/00 , G02B6/10 , G02F1/00
CPC分类号： G02B6/12002 , B82Y20/00 , G02B6/1223 , G02B6/132 , G02B6/136
摘要： A method for manufacturing multiple layers of waveguides is disclosed. Initially, a first cladding layer is deposited on a substrate, a first inner cladding layer is then deposited on the first cladding layer, and a first waveguide material is deposited on the first inner cladding layer. The first inner cladding layer and the first waveguide material are then selectively etched to form a first waveguide layer. Next, a second inner cladding layer followed by a second cladding layer are deposited on the first waveguide layer. The second inner cladding layer and the second cladding layer are removed by using a chemical-mechanical polishing process selective to the first waveguide material. A third inner cladding layer followed by a second waveguide material are deposited on the first waveguide material. The third inner cladding layer and the second waveguide material are then selectively etched to form a second waveguide layer. Finally, a fourth inner cladding layer followed by a third cladding layer are deposited on the second waveguide layer.
摘要翻译：公开了制造多层波导的方法。首先，在基板上沉积第一包层，然后在第一包层上沉积第一内包层，在第一内包层上沉积第一波导材料。然后选择性地蚀刻第一内包层和第一波导材料以形成第一波导层。接下来，在第一波导层上沉积第二内包层和第二覆层。通过使用对第一波导材料选择性的化学机械抛光工艺来除去第二内包层和第二包覆层。在第一波导材料上沉积第三内包层和第二波导材料。然后选择性地蚀刻第三内包层和第二波导材料以形成第二波导层。最后，在第二波导层上沉积第四内包层和第三覆层。

5. 发明申请

US20110036289A1 METHOD FOR GROWING GERMANIUM EPITAXIAL FILMS 有权
标题翻译：生长锗外膜的方法
公开(公告)号：US20110036289A1
公开(公告)日：2011-02-17
申请号：US12539003
申请日：2009-08-11
申请人： Daniel N. Carothers , Craig M. Hill , Andrew T.S. Pomerene , Vu A. Vu
发明人： Daniel N. Carothers , Craig M. Hill , Andrew T.S. Pomerene , Vu A. Vu
IPC分类号： C30B25/02
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02579 , H01L21/0262 , H01L21/02645 , H01L21/02658
摘要： A method for growing germanium epitaxial films is disclosed. Initially, a silicon substrate is preconditioned with hydrogen gas. The temperature of the preconditioned silicon substrate is then decreased, and germane gas is flowed over the preconditioned silicon substrate to form an intrinsic germanium seed layer. Next, a mixture of germane and phosphine gases can be flowed over the intrinsic germanium seed layer to produce an n-doped germanium seed layer. Otherwise, a mixture of diborane and germane gases can be flowed over the intrinsic germanium seed layer to produce a p-doped germanium seed layer. At this point, a bulk germanium layer can be grown on top of the doped germanium seed layer.
摘要翻译：公开了一种用于生长锗外延膜的方法。首先，用氢气预处理硅衬底。然后，预处理的硅衬底的温度降低，并且锗烷气体在预处理的硅衬底上流动以形成固有的锗种子层。接下来，可以将锗烷烃和磷化氢气体的混合物流过本征锗种子层，以产生n掺杂的锗种子层。否则，乙硼烷和锗烷气体的混合物可以流过本征锗种子层，以产生p掺杂锗种子层。此时，可以在掺杂的锗种子层的顶部上生长大块锗层。

6. 发明申请

US20100330727A1 Method for Fabricating Butt-Coupled Electro-Absorptive Modulators 有权
标题翻译：制造对接耦合电吸收调制器的方法
公开(公告)号：US20100330727A1
公开(公告)日：2010-12-30
申请号：US12523801
申请日：2008-08-29
申请人： Craig M. Hill , Andrew T.S. Pomerene
发明人： Craig M. Hill , Andrew T.S. Pomerene
IPC分类号： H01L31/0232 , H01L31/18
CPC分类号： G02F1/025
摘要： A method for fabricating butt-coupled electro-absorptive modulators is disclosed. A butt-coupled electro-absorptive modulator with minimal dislocations in the electro-absorptive material is produced by adding a dielectric spacer for lining the coupling region before epitaxially growing the SiGe or other electro-absorptive material. It has been determined that during the SiGe growth, the current process has exposed single crystal silicon at the bottom of the hole and exposed amorphous silicon on the sides. SiGe growth on the amorphous silicon is expected to have more dislocations than single crystal silicon. There should also be dislocations or fissures where the SiGe growth from the each nucleation source finally join. Thus, a dielectric sidewall can protect an exposed waveguide face from any etching from an aggressive surface preparation prior to epi growth.
摘要翻译：公开了一种制造对接耦合的电吸收调制器的方法。通过在外延生长SiGe或其他电吸收材料之前添加用于衬垫耦合区域的电介质间隔物来产生电吸收材料中具有最小位错的对接耦合电吸收调制器。已经确定，在SiGe生长期间，目前的工艺已经在孔的底部露出单晶硅并在侧面露出非晶硅。 SiGe在非晶硅上的生长预期具有比单晶硅更多的位错。也应该存在来自每个成核源的SiGe生长最终加入的位错或裂缝。因此，电介质侧壁可以在外延生长之前保护暴露的波导面不受腐蚀性表面处理的任何蚀刻。

7. 发明申请

US20100029033A1 Method for Manufacturing Vertical Germanium Detectors 失效
标题翻译：制造垂直锗探测器的方法
公开(公告)号：US20100029033A1
公开(公告)日：2010-02-04
申请号：US12517712
申请日：2008-10-20
申请人： Daniel N. Carothers , Craig M. Hill , Andrew T.S. Pomerene , Vu A. Vu , Joe Giunta , Jonathan N. Ishii
发明人： Daniel N. Carothers , Craig M. Hill , Andrew T.S. Pomerene , Vu A. Vu , Joe Giunta , Jonathan N. Ishii
IPC分类号： H01L31/0232
CPC分类号： H01L31/1808 , H01L31/105 , H01L31/1055 , Y02E10/50
摘要： An improved method for manufacturing a vertical germanium detector is disclosed. Initially, a detector window is opened through an oxide layer on a single crystalline substrate. Next, a single crystal germanium layer is grown within the detector window, and an amorphous germanium layer is grown on the oxide layer. The amorphous germanium layer is then polished and removed until only a portion of the amorphous germanium layer is located around the single crystal germanium layer. A tetraethyl orthosilicate (TEOS) layer is deposited on the amorphous germanium layer and the single crystal germanium layer. An implant is subsequently performed on the single crystal germanium layer. After an oxide window has been opened on the TEOS layer, a titanium layer is deposited on the single crystal germanium layer to form a vertical germanium detector.
摘要翻译：公开了用于制造垂直锗探测器的改进方法。最初，检测器窗口通过单晶衬底上的氧化物层开放。接下来，在检测器窗口内生长单晶锗层，并且在氧化物层上生长非晶锗层。然后抛光和去除无定形锗层，直到只有一部分非晶锗层位于单晶锗层周围。在无定形锗层和单晶锗层上沉积原硅酸四乙酯（TEOS）层。随后在单晶锗层上进行植入。在TEOS层上打开氧化物窗后，在单晶锗层上沉积钛层以形成垂直锗检测器。

8. 发明申请

US20120304919A1 Method For Growing Germanium Epitaxial Films 审中-公开
标题翻译：锗外延膜生长方法
公开(公告)号：US20120304919A1
公开(公告)日：2012-12-06
申请号：US13585931
申请日：2012-08-15
申请人： Daniel N. Carothers , Craig M. Hill , Andrew T.S. Pomerene , Vu A. Vu
发明人： Daniel N. Carothers , Craig M. Hill , Andrew T.S. Pomerene , Vu A. Vu
IPC分类号： C30B25/10
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02579 , H01L21/0262 , H01L21/02645 , H01L21/02658
摘要： A method for growing germanium epitaxial films is disclosed. Initially, a silicon substrate is preconditioned with hydrogen gas. The temperature of the preconditioned silicon substrate is then decreased, and germane gas is flowed over the preconditioned silicon substrate to form an intrinsic germanium seed layer. Next, a mixture of germane and phosphine gases can be flowed over the intrinsic germanium, seed layer to produce an n-doped germanium seed layer. Otherwise, a mixture of diborane and germane gases can be flowed over the intrinsic germanium seed layer to produce a p-doped germanium seed layer. At this point, a hulk germanium layer can be grown on top of the doped germanium seed layer.
摘要翻译：公开了一种用于生长锗外延膜的方法。首先，用氢气预处理硅衬底。然后，预处理的硅衬底的温度降低，并且锗烷气体在预处理的硅衬底上流动以形成固有的锗种子层。接下来，可以将锗烷烃和磷化氢气体的混合物流过本征锗，种子层，以产生n掺杂的锗种子层。否则，乙硼烷和锗烷气体的混合物可以流过本征锗种子层，以产生p掺杂锗种子层。此时，可以在掺杂的锗种子层的顶部生长富锗锗层。

9. 发明授权

US08513037B2 Method of integrating slotted waveguide into CMOS process 有权
标题翻译：将开槽波导集成到CMOS工艺中的方法
公开(公告)号：US08513037B2
公开(公告)日：2013-08-20
申请号：US13580872
申请日：2011-12-02
申请人： Andrew T S Pomerene , Craig M. Hill , Timothy J. Conway , Stewart L. Ocheltree
发明人： Andrew T S Pomerene , Craig M. Hill , Timothy J. Conway , Stewart L. Ocheltree
IPC分类号： H01P1/15
CPC分类号： H01L27/13 , H01L21/84 , H01L27/1463 , H01L27/14683
摘要： A method for integrating a slotted waveguide into a CMOS process is disclosed. A slot can be patterned on a SOI wafer by etching a first pad hard mask deposited over the wafer. The slot is then filled with a nitride plug material by depositing a second pad hard mask over the first pad hard mask. A waveguide in association with one or more electronic and photonic devices can also be patterned on the SOI wafer. The trenches can be filled with an isolation material and then polished. Thereafter, the first and second pad hard masks can be stripped from the wafer. The slot can once again be filled with the nitride plug material and patterned. After forming one or more electronic and photonic devices on the wafer using a standard CMOS process, a via can be opened down to the nitride plug and the nitride plug can then be removed.
摘要翻译：公开了一种将时隙波导集成到CMOS工艺中的方法。通过蚀刻沉积在晶片上的第一焊盘硬掩模，可以在SOI晶片上图案化槽。然后通过在第一焊盘硬掩模上沉积第二焊盘硬掩模，然后用氮化物塞材料填充槽。与一个或多个电子和光子器件相关联的波导也可以在SOI晶片上图案化。沟槽可以用隔离材料填充，然后抛光。此后，可以从晶片剥离第一和第二焊盘硬掩模。该槽可再次填充氮化物塞材料并图案化。在使用标准CMOS工艺在晶片上形成一个或多个电子和光子器件之后，可以将通孔向下打开到氮化物塞，然后可以去除氮化物塞。

10. 发明申请

US20120252158A1 Method for Manufacturing Lateral Germanium Detectors 失效
标题翻译：制造侧向锗探测器的方法
公开(公告)号：US20120252158A1
公开(公告)日：2012-10-04
申请号：US12521853
申请日：2008-10-27
申请人： Daniel N. Carothers , Craig M. Hill , Andrew T. S. Pomerene , Vu A. Vu , Robert Kamocsai , Timothy J. Conway
发明人： Daniel N. Carothers , Craig M. Hill , Andrew T. S. Pomerene , Vu A. Vu , Robert Kamocsai , Timothy J. Conway
IPC分类号： H01L31/18
CPC分类号： H01L27/1467
摘要： An improved method for manufacturing a lateral germanium detector is disclosed. A detector window is opened through an oxide layer to expose a doped single crystalline silicon layer situated on a substrate. Next, a single crystal germanium layer is grown within the detector window, and an amorphous germanium layer is grown on the oxide layer. The amorphous germanium layer is then polished to leave only a small portion around the single crystal germanium layer. A dielectric layer is deposited on the amorphous germanium layer and the single crystal germanium layer. Using resist masks and ion implants, multiple doped regions are formed on the single crystal germanium layer. After opening several oxide windows on the dielectric layer, a refractory metal layer is deposited on the doped regions to form multiple germanide layers.
摘要翻译：公开了用于制造侧向锗检测器的改进方法。检测器窗口通过氧化物层打开以暴露位于衬底上的掺杂单晶硅层。接下来，在检测器窗口内生长单晶锗层，并且在氧化物层上生长非晶锗层。然后抛光无定形锗层以在单晶锗层周围仅留下一小部分。介电层沉积在非晶锗层和单晶锗层上。使用抗蚀剂掩模和离子注入，在单晶锗层上形成多个掺杂区。在介电层上打开几个氧化物窗后，在掺杂区域上沉积难熔金属层以形成多个锗化物层。

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