专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07010014B1 Digital spread spectrum circuitry 有权
标题翻译：数字扩频电路
公开(公告)号：US07010014B1
公开(公告)日：2006-03-07
申请号：US09684528
申请日：2000-10-06
申请人： Andrew K. Percey , John D. Logue , F. Erich Goetting , Paul G. Hyland
发明人： Andrew K. Percey , John D. Logue , F. Erich Goetting , Paul G. Hyland
IPC分类号： H04B1/69 , H03D3/24 , H03L7/00 , H03L7/06
CPC分类号： H03L7/0814 , G06F1/10 , H03L7/07
摘要： The frequency of a skew clock signal is dithered around a base frequency, thereby enabling this clock signal to comply with FCC requirements for electromagnetic emissions within a specified window. Delay is introduced such that the clock signals exhibits slightly different frequencies in successive periods. For example, the frequency of a 100 MHz clock signal can be adjusted to have frequencies of approximately 98, 98.5, 99, 99.5, 100, 100.5, 101, 101.5, and 102 MHz during different periods. Because the frequencies are spread in 0.5 MHz increments, only three frequencies are included in any 1 MHz window. As a result, ⅔ of the energy of the clock signal is not included when determining whether the clock signal meets the FCC electromagnetic emission requirements. By spreading the frequencies above and below the base frequency in a regular manner, the average frequency of the clock signal becomes equal to the base frequency.
摘要翻译：偏移时钟信号的频率在基频周围抖动，从而使该时钟信号能够符合FCC在指定窗口内对电磁辐射的要求。引入延迟使得时钟信号在连续的周期中表现出稍微不同的频率。例如，100MHz时钟信号的频率可以在不同时段期间被调整为具有约98,98.5,99,99.5,100,150.5,101,101.5和102MHz的频率。由于频率以0.5 MHz为单位进行扩展，所以在1 MHz窗口中只能包含三个频率。因此，当确定时钟信号是否满足FCC电磁辐射要求时，不包括时钟信号的能量的2/3。通过以规则的方式扩展基频以上的频率，时钟信号的平均频率等于基频。

2. 发明授权

US06204710B1 Precision trim circuit for delay lines 失效
标题翻译：精密微调电路延时线
公开(公告)号：US06204710B1
公开(公告)日：2001-03-20
申请号：US09102730
申请日：1998-06-22
申请人： F. Erich Goetting , Paul G. Hyland , Joseph H. Hassoun
发明人： F. Erich Goetting , Paul G. Hyland , Joseph H. Hassoun
IPC分类号： H03K513
CPC分类号： H03K5/133 , H03K2005/00058 , H03K2005/00084
摘要： A precision trim circuit for a tuneable delay line is provided. The precision trim circuit provides delays greater than the base delay of the tuneable delay line. By using larger delays than conventional trim circuits, the precision trim circuit of the present invention can use components that react to process and environmental variations in the same manner as the components of the tuneable delay line. Specifically, one embodiment of the precision trim circuit comprises a first delay element providing a delay greater than or equal to the base delay of the tuneable delay line. The precision trim circuit also comprises a second delay element providing a greater delay than the first delay element. A multiplexer coupled to the first delay element and the second delay element is used to select the amount of delay provided by the precision trim circuit. Other embodiments include additional delay elements providing varying delay values.
摘要翻译：提供了一种用于可调延迟线的精密微调电路。精密微调电路提供大于可调延迟线的基本延迟的延迟。通过使用比传统的微调电路更大的延迟，本发明的精密微调电路可以以与可调延迟线的组件相同的方式使用对处理和环境变化做出反应的组件。具体地，精密微调电路的一个实施例包括提供大于或等于可调延迟线的基本延迟的延迟的第一延迟元件。精密微调电路还包括提供比第一延迟元件更大的延迟的第二延迟元件。耦合到第一延迟元件和第二延迟元件的多路复用器用于选择由精密调整电路提供的延迟量。其他实施例包括提供可变延迟值的附加延迟元件。

3. 发明授权

US06788119B1 Delay line circuit providing clock pulse width restoration in delay lock loops 有权
标题翻译：延迟线电路在延迟锁定环路中提供时钟脉冲宽度恢复
公开(公告)号：US06788119B1
公开(公告)日：2004-09-07
申请号：US10402058
申请日：2003-03-27
申请人： Paul G. Hyland , Patrick T. Lynch
发明人： Paul G. Hyland , Patrick T. Lynch
IPC分类号： H03L706
CPC分类号： H03K5/1565 , H03K5/133 , H03K2005/00156 , H03L7/0814 , H03L7/087
摘要： Delay lock loops (DLLs) that include delay line circuits with an optional clock pulse width restoration feature, and programmable delay circuits that enable the DLLs. A DLL can include optional inversions before and after at least one of the delay lines included in the DLL. Because two inversions are provided, the overall logic of the delay line is preserved. A DLL typically includes several different delay lines. Therefore, by selectively inverting the clock signal between the delay lines, the effect of each delay line on the clock pulse width can be balanced to provide an output clock signal having a pulse width closer to that of the input clock than would be achievable without the use of such selective inversion. In embodiments where the DLL forms a portion of a programmable logic device (PLD), the optional inversions can be controlled, for example, by configuration memory cells of the PLD.
摘要翻译：延迟锁定循环（DLL），包括具有可选时钟脉冲宽度恢复功能的延迟线电路，以及启用DLL的可编程延迟电路。 DLL可以包括在DLL中包括的至少一个延迟线之前和之后的可选的反转。因为提供了两个反转，所以延迟线的整体逻辑被保留。 DLL通常包括几个不同的延迟线。因此，通过选择性地反转延迟线之间的时钟信号，可以平衡每个延迟线对时钟脉冲宽度的影响，以提供具有比可以实现的脉冲宽度更接近于输入时钟的脉冲宽度的输出时钟信号，而不需要使用这种选择性反转。在DLL形成可编程逻辑器件（PLD）的一部分的实施例中，可以例如通过PLD的配置存储器单元来控制可选的反转。

4. 发明授权

US06847246B1 Method and apparatus for reducing jitter and power dissipation in a delay line 有权
标题翻译：用于减少延迟线中的抖动和功耗的方法和装置
公开(公告)号：US06847246B1
公开(公告)日：2005-01-25
申请号：US10284725
申请日：2002-10-31
申请人： Alireza S. Kaviani , Patrick T. Lynch , Paul G. Hyland , Patrick J. Crotty , Tao Pi
发明人： Alireza S. Kaviani , Patrick T. Lynch , Paul G. Hyland , Patrick J. Crotty , Tao Pi
IPC分类号： H03H11/26 , H03K5/00 , H03K5/13 , H03L7/081
CPC分类号： H03L7/0814 , H03K5/133 , H03K2005/00058 , H03K2005/00156
摘要： Method and apparatus for reducing power dissipation and jitter in a delay line is described. The delay line includes a plurality of delay elements. At least one of the plurality of delay elements includes a gate terminal configured to receive gate control signals for activating or deactivating one or more of the delay elements. The delay line further includes gate control circuitry for providing gate control signals to the gate terminal of at least one of the plurality of delay elements.
摘要翻译：描述了用于降低延迟线中的功耗和抖动的方法和装置。延迟线包括多个延迟元件。多个延迟元件中的至少一个包括被配置为接收用于激活或去激活一个或多个延迟元件的栅极控制信号的栅极端子。延迟线还包括用于向多个延迟元件中的至少一个延迟元件的栅极端子提供栅极控制信号的栅极控制电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式