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1. 发明授权

US07996646B2 Efficient encoding for detecting load dependency on store with misalignment 有权
标题翻译：高效编码，用于检测不对齐存储的负载依赖性
公开(公告)号：US07996646B2
公开(公告)日：2011-08-09
申请号：US12721164
申请日：2010-03-10
申请人： Tse-yu Yeh , Daniel C. Murray , Po-Yung Chang , Anup S. Mehta
发明人： Tse-yu Yeh , Daniel C. Murray , Po-Yung Chang , Anup S. Mehta
IPC分类号： G06F12/00
CPC分类号： G06F12/0607
摘要： In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation. The first even mask identifies bytes within the first even byte range that are written by the store memory operation, and wherein the first odd mask identifies bytes within the first odd byte range that are written by the store memory operation.
摘要翻译：在一个实施例中，装置包括包括多个条目的队列和耦合到队列的控制单元。控制单元被配置为将第一队列条目分配给存储存储器操作，并且被配置为将对应于存储存储器操作的第一偶数偏移，第一偶数掩码，第一奇数偏移和第一奇数掩码写入到第一次入场一组连续的存储器位置在逻辑上被划分为交替寻址的偶数和奇数字节范围。给定的存储器操作写入至多一个偶数字节范围和一个相邻的奇数字节范围。第一偶数偏移识别由存储器存储器操作潜在地写入的第一偶数字节范围，并且第一奇数偏移识别潜在地由存储器存储器操作写入的第一奇数字节范围。第一偶数掩模识别由存储器存储器操作写入的第一偶数字节范围内的字节，并且其中第一奇数掩码标识由存储器存储器操作写入的第一奇数字节范围内的字节。

2. 发明申请

US20080307173A1 Efficient Encoding for Detecting Load Dependency on Store with Misalignment 有权
标题翻译：高效编码，用于检测负载依赖关系，存储不对齐
公开(公告)号：US20080307173A1
公开(公告)日：2008-12-11
申请号：US11758193
申请日：2007-06-05
申请人： Tse-yu Yeh , Daniel C. Murray , Po-Yung Chang , Anup S. Mehta
发明人： Tse-yu Yeh , Daniel C. Murray , Po-Yung Chang , Anup S. Mehta
IPC分类号： G06F12/00
CPC分类号： G06F12/0607
摘要： In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation. The first even mask identifies bytes within the first even byte range that are written by the store memory operation, and wherein the first odd mask identifies bytes within the first odd byte range that are written by the store memory operation.
摘要翻译：在一个实施例中，装置包括包括多个条目的队列和耦合到队列的控制单元。控制单元被配置为将第一队列条目分配给存储存储器操作，并且被配置为将对应于存储存储器操作的第一偶数偏移，第一偶数掩码，第一奇数偏移和第一奇数掩码写入到第一次入场一组连续的存储器位置在逻辑上被划分为交替寻址的偶数和奇数字节范围。给定的存储器操作写入至多一个偶数字节范围和一个相邻的奇数字节范围。第一偶数偏移识别由存储器存储器操作潜在地写入的第一偶数字节范围，并且第一奇数偏移识别潜在地由存储器存储器操作写入的第一奇数字节范围。第一偶数掩模识别由存储器存储器操作写入的第一偶数字节范围内的字节，并且其中第一奇数掩码标识由存储器存储器操作写入的第一奇数字节范围内的字节。

3. 发明授权

US07721066B2 Efficient encoding for detecting load dependency on store with misalignment 有权
标题翻译：高效编码，用于检测不对齐存储的负载依赖性
公开(公告)号：US07721066B2
公开(公告)日：2010-05-18
申请号：US11758193
申请日：2007-06-05
申请人： Tse-yu Yeh , Daniel C. Murray , Po-Yung Chang , Anup S. Mehta
发明人： Tse-yu Yeh , Daniel C. Murray , Po-Yung Chang , Anup S. Mehta
IPC分类号： G06F12/00
CPC分类号： G06F12/0607
摘要： In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation. The first even mask identifies bytes within the first even byte range that are written by the store memory operation, and wherein the first odd mask identifies bytes within the first odd byte range that are written by the store memory operation.
摘要翻译：在一个实施例中，装置包括包括多个条目的队列和耦合到队列的控制单元。控制单元被配置为将第一队列条目分配给存储存储器操作，并且被配置为将对应于存储存储器操作的第一偶数偏移，第一偶数掩码，第一奇数偏移和第一奇数掩码写入到第一次入场一组连续的存储器位置在逻辑上被划分为交替寻址的偶数和奇数字节范围。给定的存储器操作写入至多一个偶数字节范围和一个相邻的奇数字节范围。第一偶数偏移识别由存储器存储器操作潜在地写入的第一偶数字节范围，并且第一奇数偏移识别潜在地由存储器存储器操作写入的第一奇数字节范围。第一偶数掩模识别由存储器存储器操作写入的第一偶数字节范围内的字节，并且其中第一奇数掩码标识由存储器存储器操作写入的第一奇数字节范围内的字节。

4. 发明授权

US08117404B2 Misalignment predictor 有权
标题翻译：对准预测器
公开(公告)号：US08117404B2
公开(公告)日：2012-02-14
申请号：US11200771
申请日：2005-08-10
申请人： Tse-Yu Yeh , Po-Yung Chang , Eric Hao
发明人： Tse-Yu Yeh , Po-Yung Chang , Eric Hao
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/30145 , G06F9/3832 , G06F9/3861
摘要： In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the processor to execute the memory operation is dependent on whether or not the circuit predicts the memory operation as misaligned. In another embodiment, a misalignment predictor is coupled to receive an indication of a memory operation, and comprises a memory and a control circuit coupled to the memory. The memory is configured to store a plurality of indications of memory operations previously detected as misaligned during execution in a processor. The control circuit is configured to predict whether or not a memory operation is misaligned responsive to a comparison of the received indication and the plurality of indications stored in the memory.
摘要翻译：在一个实施例中，处理器包括耦合以接收要在处理器中执行的存储器操作的指示的电路。电路被配置为预测存储器操作是否不对准。由处理器执行的执行存储器操作的多个访问取决于电路是否将存储器操作预测为未对准。在另一个实施例中，未对准预测器被耦合以接收存储器操作的指示，并且包括耦合到存储器的存储器和控制电路。存储器被配置为存储先前在处理器中执行期间被检测为未对准的存储器操作的多个指示。控制电路被配置为响应于所接收的指示与存储在存储器中的多个指示的比较来预测存储器操作是否失准。

5. 发明申请

US20080086622A1 Replay reduction for power saving 有权
标题翻译：节电减重
公开(公告)号：US20080086622A1
公开(公告)日：2008-04-10
申请号：US11546223
申请日：2006-10-10
申请人： Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
发明人： Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
IPC分类号： G06F9/30
CPC分类号： G06F9/3842
摘要： In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledge indication is asserted that corresponds to an identified replay case of the subset.
摘要翻译：在一个实施例中，处理器包括被配置为发出要执行的第一指令操作和耦合到调度器的执行核心的调度器。配置为执行第一指令操作，执行核心包括被配置为响应于检测多个重放情况中的至少一个而使第一指令操作重放的多个重放源。调度器被配置为禁止在多个重放情况的子集的重放之后发出第一指令操作。调度器被耦合以接收对应于子集中的多个重播案例中的每一个的确认指示，并且被配置为禁止发出第一指令操作，直到确认对应于所识别的该子集的重放情况为止的确认指示为止。

6. 发明申请

US20080086594A1 Uncacheable load merging 审中-公开
标题翻译：不可加载的负载合并
公开(公告)号：US20080086594A1
公开(公告)日：2008-04-10
申请号：US11545825
申请日：2006-10-10
申请人： Po-Yung Chang , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
发明人： Po-Yung Chang , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F9/30043 , G06F9/3826 , G06F12/0888 , Y02D10/13
摘要： In one embodiment, a processor comprises a buffer and a control unit coupled to the buffer. The buffer is configured to store requests to be transmitted on an interconnect on which the processor is configured to communicate. The buffer is coupled to receive a first uncacheable load request having a first address. The control unit is configured to merge the first uncacheable load request with a second uncacheable load request that is stored in the buffer responsive to a second address of the second load request matching the first address within a granularity. A single transaction on the interconnect is used for both the first and second uncacheable load requests, if merged. Separate transactions on the interconnect are used for each of the first and second uncacheable load requests if not merged.
摘要翻译：在一个实施例中，处理器包括耦合到缓冲器的缓冲器和控制单元。缓冲器被配置为存储要在处理器配置为进行通信的互连上发送的请求。缓冲器被耦合以接收具有第一地址的第一不可缓存的加载请求。所述控制单元被配置为将所述第一不可缓存的加载请求与存储在所述缓冲器中的第二不可缓存的加载请求进行合并，所述第二不可缓存的加载请求响应于在粒度内与所述第一地址匹配的第二加载请求的第二地址。如果合并，互连上的单个事务将用于第一个和第二个不可缓存的加载请求。对于第一和第二不可缓存的加载请求中的每一个，如果不合并，则互连上的单独事务将被使用。

7. 发明授权

US07162613B2 Mechanism for processing speculative LL and SC instructions in a pipelined processor 失效
标题翻译：在流水线处理器中处理推测性LL和SC指令的机制
公开(公告)号：US07162613B2
公开(公告)日：2007-01-09
申请号：US11046454
申请日：2005-01-28
申请人： Tse-Yu Yeh , Po-Yung Chang , Mark H. Pearce , Zongjian Chen
发明人： Tse-Yu Yeh , Po-Yung Chang , Mark H. Pearce , Zongjian Chen
IPC分类号： G06F9/312
CPC分类号： G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3834 , G06F9/3842 , G06F9/3861 , G06F9/3867
摘要： A processor includes a first circuit and a second circuit. The first circuit is configured to provide a first indication of whether or not at least one reservation is valid in the processor. A reservation is established responsive to processing a load-linked instruction, which is a load instruction that is architecturally defined to establish the reservation. A valid reservation is indicative that one or more bytes indicated by the target address of the load-linked instruction have not been updated since the reservation was established. The second circuit is coupled to receive the first indication. Responsive to the first indication indicating no valid reservation, the first circuit is configured to select a speculative load-linked instruction for issued. The second circuit is configured not to select the speculative load-linked instruction for issue responsive to the first indication indicating the at least one valid reservation. A method is also contemplated.
摘要翻译：一种处理器包括第一电路和第二电路。第一电路被配置为提供在处理器中至少一个预留是否有效的第一指示。响应于处理负载链接指令来建立预留，负载指令是建筑上定义用于建立预留的加载指令。有效的预约指示由保留建立以来，由负载链接指令的目标地址指示的一个或多个字节未被更新。第二电路被耦合以接收第一指示。响应于第一指示，不指示有效预约，第一电路被配置为选择用于发出的推测性加载链接指令。第二电路被配置为不响应于指示至少一个有效预留的第一指示来选择用于发出的推测性加载链接指令。也考虑了一种方法。

8. 发明申请

US20120110392A1 MISALIGNMENT PREDICTOR 有权
标题翻译：失业预测者
公开(公告)号：US20120110392A1
公开(公告)日：2012-05-03
申请号：US13345260
申请日：2012-01-06
申请人： Tse-Yu Yeh , Po-Yung Chang , Eric Hao
发明人： Tse-Yu Yeh , Po-Yung Chang , Eric Hao
IPC分类号： G06F11/30
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/30145 , G06F9/3832 , G06F9/3861
摘要： In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the processor to execute the memory operation is dependent on whether or not the circuit predicts the memory operation as misaligned. In another embodiment, a misalignment predictor is coupled to receive an indication of a memory operation, and comprises a memory and a control circuit coupled to the memory. The memory is configured to store a plurality of indications of memory operations previously detected as misaligned during execution in a processor. The control circuit is configured to predict whether or not a memory operation is misaligned responsive to a comparison of the received indication and the plurality of indications stored in the memory.
摘要翻译：在一个实施例中，处理器包括耦合以接收要在处理器中执行的存储器操作的指示的电路。电路被配置为预测存储器操作是否不对准。由处理器执行的执行存储器操作的多个访问取决于电路是否将存储器操作预测为未对准。在另一个实施例中，未对准预测器被耦合以接收存储器操作的指示，并且包括耦合到存储器的存储器和控制电路。存储器被配置为存储先前在处理器中执行期间被检测为未对准的存储器操作的多个指示。控制电路被配置为响应于所接收的指示与存储在存储器中的多个指示的比较来预测存储器操作是否失准。

9. 发明授权

US06877085B2 Mechanism for processing speclative LL and SC instructions in a pipelined processor 失效
标题翻译：在流水线处理器中处理特定LL和SC指令的机制
公开(公告)号：US06877085B2
公开(公告)日：2005-04-05
申请号：US10068286
申请日：2002-02-06
申请人： Tse-Yu Yeh , Po-Yung Chang , Mark H. Pearce , Zongjian Chen
发明人： Tse-Yu Yeh , Po-Yung Chang , Mark H. Pearce , Zongjian Chen
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3834 , G06F9/3842 , G06F9/3861 , G06F9/3867
摘要： A processor includes a first circuit and a second circuit. The first circuit is configured to provide a first indication of whether or not at least one reservation is valid in the processor. A reservation is established responsive to processing a load-linked instruction, which is a load instruction that is architecturally defined to establish the reservation. A valid reservation is indicative that one or more bytes indicated by the target address of the load-linked instruction have not been updated since the reservation was established. The second circuit is coupled to receive the first indication. Responsive to the first indication indicating no valid reservation, the first circuit is configured to select a speculative load-linked instruction for issued. The second circuit is configured not to select the speculative load-linked instruction for issue responsive to the first indication indicating the at least one valid reservation. A method is also contemplated.
摘要翻译：处理器包括第一电路和第二电路。第一电路被配置为提供在处理器中至少一个预留是否有效的第一指示。响应于处理负载链接指令来建立预留，负载指令是建筑上定义用于建立预留的加载指令。有效的预约指示由保留建立以来，由负载链接指令的目标地址指示的一个或多个字节未被更新。第二电路被耦合以接收第一指示。响应于第一指示，不指示有效预约，第一电路被配置为选择用于发出的推测性加载链接指令。第二电路被配置为不响应于指示至少一个有效预留的第一指示来选择用于发出的推测性加载链接指令。也考虑了一种方法。

10. 发明授权

US08255670B2 Replay reduction for power saving 有权
标题翻译：节电减重
公开(公告)号：US08255670B2
公开(公告)日：2012-08-28
申请号：US12619751
申请日：2009-11-17
申请人： Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
发明人： Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3842
摘要： In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledgement indication is asserted that corresponds to an identified replay case of the subset.
摘要翻译：在一个实施例中，处理器包括被配置为发出要执行的第一指令操作和耦合到调度器的执行核心的调度器。配置为执行第一指令操作，执行核心包括被配置为响应于检测多个重放情况中的至少一个而使第一指令操作重放的多个重放源。调度器被配置为禁止在多个重放情况的子集的重放之后发出第一指令操作。调度器被耦合以接收对应于子集中的多个重播案例中的每一个的确认指示，并且被配置为禁止发出第一指令操作，直到确认对应于该子集的所识别的重放大小写的确认指示为止。

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