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1. 发明授权

US5499356A Method and apparatus for a multiprocessor resource lockout instruction 失效
标题翻译：多处理器资源锁定指令的方法和装置
公开(公告)号：US5499356A
公开(公告)日：1996-03-12
申请号：US173923
申请日：1993-12-28
申请人： Roger E. Eckert , Richard E. Hessel , Andrew E. Phelps , George A. Spix , Jimmie R. Wilson
发明人： Roger E. Eckert , Richard E. Hessel , Andrew E. Phelps , George A. Spix , Jimmie R. Wilson
IPC分类号： G06F9/30 , G06F9/312 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F9/46 , G06F11/36 , G06F15/173 , G06F15/78 , G06F15/80 , G06F12/14
CPC分类号： G06F15/8076 , G06F15/17381 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/3004 , G06F9/30069 , G06F9/30087 , G06F9/30094 , G06F9/30101 , G06F9/3012 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3824 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/526 , G06F2209/521
摘要： A method and apparatus for providing a resource lockout mechanism in a shared memory, multiprocessor system that is capable of performing both a read and write operation during the same memory operation. The load and flag instruction of the present invention can execute a read operation, followed by a write operation of a preselected flag value to the same memory location during the same memory operation. The load and flag instruction is particularly useful as a resource lockout mechanism for use in Monte Carlo applications.
摘要翻译：一种用于在共享存储器中提供资源锁定机制的方法和装置，该多处理器系统能够在同一存储器操作期间同时执行读取和写入操作。本发明的加载和标志指令可以在相同的存储器操作期间执行读取操作，随后将预选标志值写入同一个存储器位置。加载和标志指令特别适用于在蒙特卡罗应用程序中使用的资源锁定机制。

2. 发明授权

US5208914A Method and apparatus for non-sequential resource access 失效
标题翻译：用于非顺序资源访问的方法和装置
公开(公告)号：US5208914A
公开(公告)日：1993-05-04
申请号：US535786
申请日：1990-06-11
申请人： Jimmie R. Wilson , Douglas R. Beard , Steve S. Chen , Roger E. Eckert , Richard E. Hessel , Andrew E. Phelps , Alexander A. Silbey , Brian D. Vanderwarn
发明人： Jimmie R. Wilson , Douglas R. Beard , Steve S. Chen , Roger E. Eckert , Richard E. Hessel , Andrew E. Phelps , Alexander A. Silbey , Brian D. Vanderwarn
IPC分类号： G06F9/46 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F12/00 , G06F15/16 , G06F15/173 , G06F15/177 , G06F15/78 , G06F15/80
CPC分类号： G06F15/17375 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/30094 , G06F9/3013 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857
摘要： A method and apparatus for non-sequential access to shared resources in a multiple requestor system uses a variety of tags to effectively re-order the data at its destination. In simplest form, the tag directs switching logic to where in a buffer to locate another tag for direction information or where in a buffer or processor (register) to put the response associated with the tag. For example, loading data from memory requires that the requestor provide a request signal, an address, and a request tag. The request signal validates the address and request tag. The address specifies the location of the requested data in memory. The request tag specifies where to put the data when it is returned to the processor. The switching logic for the requestor includes a tag queue for storing the request tags associated with the resource requests, logic means for associating the respective request tag from the tag queue with a resource response, and means for returning the resource response and respective request tag to the requestor. The switching logic associated with the shared resource includes switching means to route the request into and out of the shared resource, control logic to correctly route the request, logic to handle multiple decision requests, and logic to store or retrieve the ultimate data entity being requested.
摘要翻译：用于在多请求者系统中非顺序访问共享资源的方法和装置使用各种标签来有效地重新排序其目的地的数据。以最简单的形式，标签将切换逻辑引导到缓冲器中的哪个位置，以定位用于方向信息的另一个标签，或者在缓冲器或处理器（寄存器）中放置与标签相关联的响应的位置。例如，从存储器加载数据要求请求者提供请求信号，地址和请求标签。请求信号验证地址和请求标签。该地址指定所请求的数据在内存中的位置。请求标签指定在将数据返回到处理器时放置数据的位置。用于请求者的切换逻辑包括用于存储与资源请求相关联的请求标签的标记队列，用于将来自标签队列的相应请求标签与资源响应相关联的逻辑装置，以及用于将资源响应和相应请求标签返回到请求者。与共享资源相关联的切换逻辑包括将请求路由到共享资源和从共享资源引出的切换装置，控制逻辑以正确路由请求，处理多个决策请求的逻辑以及存储或检索被请求的最终数据实体的逻辑。

3. 发明授权

US5381536A Method and apparatus for separate mark and wait instructions for processors having multiple memory ports 失效
标题翻译：用于具有多个存储器端口的处理器的单独标记和等待指令的方法和装置
公开(公告)号：US5381536A
公开(公告)日：1995-01-10
申请号：US249084
申请日：1994-05-25
申请人： Andrew E. Phelps , Roger E. Eckert , Richard E. Hessel
发明人： Andrew E. Phelps , Roger E. Eckert , Richard E. Hessel
IPC分类号： G06F9/38 , G06F11/36 , G06F12/00 , G06F13/00 , G06F15/16
CPC分类号： G06F9/3836 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3834
摘要： The present invention provides a method and apparatus for handling memory hazards in processors having multiple memory ports wherein the operation of marking of the memory requests that may be related to a memory hazard is separated from the operation of waiting for the memory hazard to clear. The separation of the operation of marking of memory hazards from the operation of waiting for memory hazards to clear allows a compiler to schedule other instructions, as well as other memory operations not directed to the memory location involved in the memory hazard sequence, during the time between the operations of marking and waiting for the memory hazard to clear. The waiting period ends once it is clear that the marked memory requests will execute in the order in which they were issued.
摘要翻译：本发明提供一种用于处理具有多个存储器端口的处理器中的存储器危险的方法和装置，其中可能与存储器危险有关的存储器请求的标记操作与等待存储器危险清除的操作分离。将记忆危害的标记操作与等待记忆危害的操作分开清除允许编译器在时间间隔内调度其他指令以及其他指令，而不是指向存储器危险序列中涉及的存储器位置的其他存储器操作在标记操作和等待记忆危害之间清除。等待期结束，一旦清楚的是，标记的内存请求将按照发出的顺序执行。

4. 发明授权

US5168570A Method and apparatus for a multiple request toggling priority system 失效
标题翻译：多重请求切换优先级系统的方法和装置
公开(公告)号：US5168570A
公开(公告)日：1992-12-01
申请号：US536417
申请日：1990-06-11
申请人： Roger E. Eckert , Andrew E. Phelps
发明人： Roger E. Eckert , Andrew E. Phelps
IPC分类号： G06F9/46 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F13/14 , G06F13/362 , G06F15/16 , G06F15/173 , G06F15/177 , G06F15/78 , G06F15/80
CPC分类号： G06F8/433 , G06F13/14 , G06F13/362 , G06F15/17368 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/45 , G06F9/30021 , G06F9/30094 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855
摘要： A multiple request toggling (MRT) arbitration system for prioritizing requests to a set of shared resources by multiple requestors, especially requests by multiple processors to shared resources in a multiprocessor system. The MRT arbitration system assigns priority to multiple requests on a first-come, first-serve basis with the priority of multiple simultaneous requests being resolved through an arbitration network.
摘要翻译：多请求切换（MRT）仲裁系统，用于将请求优先于多个请求者的一组共享资源，特别是多处理器对多处理器系统中的共享资源的请求。 MRT仲裁系统以先到先得的优先级分配多个同时请求的优先级，通过仲裁网络解决。

5. 发明授权

US07376803B1 Page stream sorter for DRAM systems 有权
标题翻译： DRAM系统的页面流分类器
公开(公告)号：US07376803B1
公开(公告)日：2008-05-20
申请号：US10969683
申请日：2004-10-19
申请人： Roger E. Eckert
发明人： Roger E. Eckert
IPC分类号： G06F12/00
CPC分类号： G06F13/1626
摘要： Circuits, methods, and apparatus for reordering memory access requests in a manner that reduces the number of page misses and thus increases effective memory bandwidth. An exemplary embodiment of the present invention uses an exposed FIFO structure. This FIFO is an n-stage bubble compressing FIFO that preserves the order of requests but allows bypassing to avoid page misses and their resulting delays. A specific embodiment exploits DRAM page locality by maintaining a set of history registers that track the last bank and row usage. Embodiments of the present invention may limit the number of times a request may be bypassed by incrementing an associated bypass counter each time the request is bypassed. Further, to avoid continuous page misses that may occur if requests alternate between two rows, a hold-off counter may be implemented.
摘要翻译：用于重新排序存储器访问请求的电路，方法和装置，以减少页面未命中的数量并因此增加有效的存储器带宽。本发明的示例性实施例使用暴露的FIFO结构。该FIFO是一个n级气泡压缩FIFO，它保留了请求的顺序，但允许旁路以避免页错误及其导致的延迟。具体实施例通过维护跟踪最后一个行和行使用的一组历史寄存器来利用DRAM页面位置。本发明的实施例可以通过在每次绕过请求时增加相关联的旁路计数器来限制请求可以绕过的次数。此外，为了避免如果请求在两行之间交替可能发生的连续的页面错误，可以实现一个暂停计数器。

6. 发明授权

US5197130A Cluster architecture for a highly parallel scalar/vector multiprocessor system 失效
标题翻译：高分辨率/矢量多媒体系统的集群架构
公开(公告)号：US5197130A
公开(公告)日：1993-03-23
申请号：US459083
申请日：1989-12-29
申请人： Steve S. Chen , Frederick J. Simmons , George A. Spix , Jimmie R. Wilson , Edward C. Miller , Roger E. Eckert , Douglas R. Beard
发明人： Steve S. Chen , Frederick J. Simmons , George A. Spix , Jimmie R. Wilson , Edward C. Miller , Roger E. Eckert , Douglas R. Beard
IPC分类号： G06F12/06 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/16 , G06F15/173 , G06F15/78 , G06F15/80 , G06F17/16
CPC分类号： G06F9/30087 , G06F11/3632 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/3004 , G06F9/30094 , G06F9/3013 , G06F9/30138 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3816 , G06F9/3828 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3846 , G06F9/3855 , G06F9/3857 , G06F9/3875 , G06F9/3885
摘要： A cluster architecture for a highly parallel multiprocessor computer processing system is comprised of one or more clusters of tightly-coupled, high-speed processors capable of both vector and scalar parallel processing that can symmetrically access shared resources associated with the cluster, as well as the shared resources associated with other clusters.
摘要翻译：用于高度并行多处理器计算机处理系统的集群架构由一个或多个紧密耦合的高速处理器群组成，能够对向地访问与集群相关联的共享资源的向量和标量并行处理，以及与其他集群相关联的共享资源。

7. 发明授权

US5561784A Interleaved memory access system having variable-sized segments logical address spaces and means for dividing/mapping physical address into higher and lower order addresses 失效
标题翻译：具有可变大小段逻辑地址空间的交错存储器存取系统以及用于将物理地址分割/映射成更高和更低地址的装置
公开(公告)号：US5561784A
公开(公告)日：1996-10-01
申请号：US268660
申请日：1994-06-29
申请人： Steve S. Chen , Frederick J. Simmons , George A. Spix , Jimmie R. Wilson , Edward C. Miller , Roger E. Eckert , Douglas R. Beard
发明人： Steve S. Chen , Frederick J. Simmons , George A. Spix , Jimmie R. Wilson , Edward C. Miller , Roger E. Eckert , Douglas R. Beard
IPC分类号： G06F12/06 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/16 , G06F15/173 , G06F15/78 , G06F15/80 , G06F17/16 , G06F9/34 , G06F12/10
CPC分类号： G06F9/30087 , G06F11/3632 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/3004 , G06F9/30094 , G06F9/3013 , G06F9/30138 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3816 , G06F9/3828 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3846 , G06F9/3855 , G06F9/3857 , G06F9/3875 , G06F9/3885
摘要： A method of accessing common memory in a cluster architecture for a highly parallel multiprocessor scaler/factor computer system using a plurality of segment registers in which is first determined whether a logical address is within a start and end range as defined by the segment registers and then relocating the logical address to a physical address using a displacement value in another segment register.
摘要翻译：一种使用多个段寄存器的高度并行的多处理器缩放器/因子计算机系统的集群架构中访问公共存储器的方法，其中首先确定逻辑地址是否在由段寄存器定义的开始和结束范围内，然后使用另一个段寄存器中的位移值将逻辑地址重定位到物理地址。

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