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1. 发明授权

US07406585B2 Data processing system having an external instruction set and an internal instruction set 失效
标题翻译：数据处理系统具有外部指令集和内部指令集
公开(公告)号：US07406585B2
公开(公告)日：2008-07-29
申请号：US10609538
申请日：2003-07-01
申请人： Andrew Christopher Rose , Krisztian Flautner
发明人： Andrew Christopher Rose , Krisztian Flautner
IPC分类号： G06F9/30
CPC分类号： G06F9/30174 , G06F9/3808 , G06F9/3836 , G06F9/3844 , G06F9/3861
摘要： There is provided a system havingan execution core operable to execute internal instructions.A translation buffer is operable to store a plurality of internal instruction blocks of one or more internal instructions where the internal instruction blocks are a dynamic translation of respective external instruction blocks of one or more external instructions.A remapper is responsive to an execution request for an external instruction that is within one of said external instruction blocks to identify a corresponding internal instruction block stored within said translation buffer. Thus one or more internal instructions from said corresponding internal instruction block can be supplied to execution core.
摘要翻译：提供了一种具有可执行内部指令的执行核心的系统。翻译缓冲器可操作以存储一个或多个内部指令的多个内部指令块，其中内部指令块是一个或多个外部指令的相应外部指令块的动态转换。再映射器响应于在所述外部指令块之一内的外部指令的执行请求，以识别存储在所述转换缓冲器内的对应的内部指令块。因此，可以将来自所述对应的内部指令块的一个或多个内部指令提供给执行核心。

2. 发明授权

US09223677B2 Generation of trace data in a multi-processor system 有权
公开(公告)号：US09223677B2
公开(公告)日：2015-12-29
申请号：US12155926
申请日：2008-06-11
申请人： Andrew Brookfield Swaine , Michael John Williams , David Kevin Hart , Andrew Christopher Rose
发明人： Andrew Brookfield Swaine , Michael John Williams , David Kevin Hart , Andrew Christopher Rose
IPC分类号： G06F11/34 , G06F11/36
CPC分类号： G06F11/348 , G06F11/3636
摘要： A data processing apparatus is provided having a plurality of processing circuits each having access to a memory. Tracing circuitry is provided for generating a stream of trace data for generating a stream of trace data corresponding to at least one of the plurality of processing circuits. Selection circuitry is provided to enable selective switching of the tracing circuitry from generating a first trace data stream corresponding to a first one of the plurality of processing circuits generating a second different trace data stream corresponding to a different one of the plurality of processing circuits. The selective switching is performed in dependence upon processing state information associating with one or more of the plurality of processing circuits. A corresponding method and computer program product are also provided.

3. 发明授权

US08621336B2 Error correction in a set associative storage device 有权
公开(公告)号：US08621336B2
公开(公告)日：2013-12-31
申请号：US12222085
申请日：2008-08-01
申请人： Simon John Craske , Andrew Christopher Rose , Paul Stanley Hughes , Antony John Penton , Richard York , Simon Andrew Ford , Stuart David Biles , Alex James Waugh
发明人： Simon John Craske , Andrew Christopher Rose , Paul Stanley Hughes , Antony John Penton , Richard York , Simon Andrew Ford , Stuart David Biles , Alex James Waugh
IPC分类号： G06F11/00
CPC分类号： G06F11/1064
摘要： A data processing apparatus is provided comprising processing circuitry for performing data processing operations, a set associative storage device for storing data values for access by the processing circuitry when performing data processing operations, error detection circuitry for performing, for each access to the storage device, an error detection operation on the data value accessed, and maintenance circuitry associated with the storage device for performing one or more maintenance operations. The processing circuitry is arranged to issue an error detection maintenance request to the maintenance circuitry specifying at least one specific physical location within the storage device, and the maintenance circuitry is responsive to the error detection maintenance request to perform at least one dummy access to the at least one specific physical location within the storage device and to provide the processing circuitry with error status information derived from the error detection operation performed by the error detection circuitry in respect of said at least one dummy access.

4. 发明申请

US20100250802A1 Data processing apparatus and method for performing hazard detection 有权
标题翻译：用于进行危害检测的数据处理装置和方法
公开(公告)号：US20100250802A1
公开(公告)日：2010-09-30
申请号：US12382939
申请日：2009-03-26
申请人： Alex James Waugh , Andrew Christopher Rose
发明人： Alex James Waugh , Andrew Christopher Rose
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F13/4022
摘要： A data processing apparatus and method are provided for performing hazard detection in respect of a series of access requests issued by processing circuitry for handling by one or more slave devices. The series of access requests include one or more write access requests, each write access request specifying a write operation to be performed by an addressed slave device, and each issued write access request being a pending write access request until the write operation has been completed by the addressed slave device. Hazard detection circuitry comprises a pending write access history storage having at least one buffer and at least one counter for keeping a record of each pending write access request. Update circuitry is responsive to receipt of a write access request to be issued by the processing circuitry, to perform an update process to identify that write access request as a pending write access request in one of the buffers, and if the identity of another pending write access request is overwritten by that update process, to increment a count value in one of the counters. On completion of each write access request by the addressed slave device, the update circuitry performs a further update process to remove the record of that completed write access request from the pending write access history storage. Hazard checking circuitry is then responsive to at least a subset of the access requests to be issued by the processing circuitry, to reference the pending write access history storage in order to determine whether a hazard condition occurs. The manner in which the update circuitry uses a combination of buffers and counters to keep a record of each pending write access request provides improved performance with respect to known prior art techniques, without the hardware cost that would be associated with increasing the number of buffers.
摘要翻译：提供了一种数据处理装置和方法，用于对由一个或多个从设备处理的处理电路发出的一系列访问请求进行危险检测。一系列访问请求包括一个或多个写访问请求，每个写访问请求指定要由寻址的从设备执行的写操作，并且每个发出的写访问请求是待处理写访问请求，直到写操作已经被寻址的从设备。危险检测电路包括具有至少一个缓冲器和至少一个用于保持每个未决写入访问请求的记录的计数器的待决写入访问历史存储器。更新电路响应于由处理电路发出的写入访问请求的接收，以执行更新处理以将该写入访问请求识别为缓冲器之一中的待决写入访问请求，并且如果另一待处理写入的标识访问请求被该更新过程覆盖，以增加其中一个计数器中的计数值。在由所寻址的从设备完成每次写入访问请求后，更新电路执行进一步的更新处理，以从挂起的写入访问历史存储中移除该完成的写访问请求的记录。危害检查电路然后对由处理电路发出的访问请求的至少一个子集作出响应，以引用待处理写入访问历史存储，以便确定是否发生危险状况。更新电路使用缓冲器和计数器的组合来保持每个待处理写入访问请求的记录的方式提供了关于已知的现有技术的改进的性能，而没有与增加缓冲器数量相关联的硬件成本。

5. 发明申请

US20090164727A1 Handling of hard errors in a cache of a data processing apparatus 有权
公开(公告)号：US20090164727A1
公开(公告)日：2009-06-25
申请号：US12004476
申请日：2007-12-21
申请人： Antony John Penton , Alex James Waugh , Andrew Christopher Rose , Paul Stanley Hughes
发明人： Antony John Penton , Alex James Waugh , Andrew Christopher Rose , Paul Stanley Hughes
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F11/1064 , G11C15/00 , G11C29/42 , G11C29/76 , G11C2029/0409 , G11C2029/0411
摘要： A data processing apparatus and method are provided for handling hard errors occurring in a cache of the data processing apparatus. The cache storage comprising data storage having a plurality of cache lines for storing data values, and address storage having a plurality of entries, with each entry identifying for an associated cache line an address indication value, and each entry having associated error data. In response to an access request, a lookup procedure is performed to determine with reference to the address indication value held in at least one entry of the address storage whether a hit condition exists in one of the cache lines. Further, error detection circuitry determines with reference to the error data associated with the at least one entry of the address storage whether an error condition exists for that entry. Additionally, cache location avoid storage is provided having at least one record, with each record being used to store a cache line identifier identifying a specific cache line. On detection of the error condition, one of the records in the cache location avoid storage is allocated to store the cache line identifier for the specific cache line associated with the entry for which the error condition was detected. Further, the error detection circuitry causes a clean and invalidate operation to be performed in respect of the specific cache line, and the access request is then re-performed. The cache access circuitry is arranged to exclude any specific cache line identified in the cache location avoid storage from the lookup procedure. This mechanism provides a very simple and effective mechanism for handling hard errors that manifest themselves within a cache during use, so as to ensure correct operation of the cache in the presence of such hard errors. Further, the technique can be employed not only in association with write through caches but also write back caches, thus providing a very flexible solution.

6. 发明申请

US20080040592A1 Control of a branch target cache within a data processing system 失效
标题翻译：控制数据处理系统内的分支目标缓存
公开(公告)号：US20080040592A1
公开(公告)日：2008-02-14
申请号：US11501920
申请日：2006-08-10
申请人： Vladimir Vasekin , Stuart David Biles , Andrew Christopher Rose , Wilco Dijkstra
发明人： Vladimir Vasekin , Stuart David Biles , Andrew Christopher Rose , Wilco Dijkstra
IPC分类号： G06F15/00
CPC分类号： G06F12/0875 , G06F9/30058 , G06F9/30181 , G06F9/3806 , G06F12/0862 , G06F2212/6028 , Y02D10/13
摘要： A data processing system includes an instruction fetching circuit 2, an instruction queue 4 and further processing circuits 6. A branch target cache, which maybe a branch target address cache 8, a branch target instruction cache 10 or both, is used to store branch target addresses or blocks of instructions starting at the branch target respectively. A control circuit 12 is responsive to the contents of the instruction queue 4 when a branch instruction is encountered to determine whether or not storage resources within the branch target cache 8, 10 should be allocated to that branch instruction. Storage resources within the branch target cache 8, 10 will be allocated when the number of program instructions within the instruction queue is below a threshold number and/or the estimated execution time of the program instructions is below a threshold time.
摘要翻译：数据处理系统包括指令提取电路2，指令队列4和其他处理电路6。分支目标高速缓存（分支目标地址高速缓存8，分支目标指令高速缓存10或两者）分别用于存储从分支目标开始的分支目标地址或指令块。当遇到分支指令时，控制电路12响应于指令队列4的内容，以确定分支目标高速缓存8,10中的存储资源是否应被分配给该分支指令。当指令队列内的程序指令数量低于阈值数量和/或程序指令的估计执行时间低于阈值时间时，将分配分支目标缓存器8,10内的存储资源。

7. 发明授权

US07000094B2 Storing stack operands in registers 有权
标题翻译：将堆栈操作数存储在寄存器中
公开(公告)号：US07000094B2
公开(公告)日：2006-02-14
申请号：US09887560
申请日：2001-06-25
申请人： Edward Colles Nevill , Andrew Christopher Rose
发明人： Edward Colles Nevill , Andrew Christopher Rose
IPC分类号： G06F9/30
CPC分类号： G06F9/4843 , G06F9/30 , G06F9/30134 , G06F9/30149 , G06F9/30174 , G06F9/3802 , G06F9/3814 , G06F9/3853 , G06F9/3861
摘要： A data processing apparatus includes a processor core having a bank of registers. The bank of registers include a set of registers that are used for the storage of stack operands. Instructions from a second instruction set specifying stack operands are translated by an instruction translator into instructions of a first instruction set (or control signals corresponding to those instructions) specifying register operands. These translated instructions are then executed by the processor core. The instruction translator has multiple mapping states for controlling which registers corresponding to which stack operands within the stack. Changes between mapping states are carried out in dependence of stack operands being added to or removed from the set of registers.
摘要翻译：数据处理装置包括具有一组寄存器的处理器核心。寄存器组包括一组用于存储堆栈操作数的寄存器。来自指定栈操作数的第二指令集的指令由指令转换器转换成指定寄存器操作数的第一指令集（或对应于那些指令的控制信号）的指令。这些翻译的指令然后由处理器核心执行。指令转换器具有多个映射状态，用于控制对应于栈内哪个堆栈操作数的寄存器。映射状态之间的变化是根据添加到寄存器组中或从该组寄存器中移除的堆栈操作数进行的。

8. 发明授权

US06958718B2 Table lookup operation within a data processing system 有权
公开(公告)号：US06958718B2
公开(公告)日：2005-10-25
申请号：US10889217
申请日：2004-07-13
申请人： Dominic Hugo Symes , Simon Ford , Andrew Christopher Rose
发明人： Dominic Hugo Symes , Simon Ford , Andrew Christopher Rose
IPC分类号： G06F9/38 , G06F7/00 , G06F9/00 , G06F9/30 , G06F9/305 , G06F9/312 , G06F9/318 , G06F9/35 , G06F9/355 , H03M7/00
CPC分类号： G06F9/3004 , G06F9/30181 , G06F9/342 , G06F9/383
摘要： A table lookup extension instruction is provided in which index values stored within an index register D2 are used to select data elements stored within one or more table registers D0, D1 for storage into corresponding positions within a result register D3. Out-of-range index values result in the corresponding locations within the result register being left unchanged U. In this way, an offset can be applied to index values held and then those index values reused with the table registers D0, D1 being reloaded with a different portion of a table so as to give the effect of a larger table than can be directly supported by the number of table registers available.

9. 发明授权

US06532553B1 Debugging data processing systems 有权
标题翻译：调试数据处理系统
公开(公告)号：US06532553B1
公开(公告)日：2003-03-11
申请号：US09407846
申请日：1999-09-29
申请人： David John Gwilt , Andrew Christopher Rose , Peter Guy Middleton , David Michael Bull
发明人： David John Gwilt , Andrew Christopher Rose , Peter Guy Middleton , David Michael Bull
IPC分类号： H02H305
CPC分类号： G06F11/3636 , G06F9/30003 , G06F9/3005
摘要： A data processing system is provided having a main processor 4 and a coprocessor 26. When in a debug mode, the main processor 4 and the coprocessor 26 are supplied with different instructions. The coprocessor 26 is supplied with a coprocessor debug data generation instruction (MCR) whilst the main processor 4 is supplied with a main processor data capture instruction (LDR). The coprocessor 26 responds to the MCR instruction by controlling debug data representing state of the data processing apparatus 2 to be placed upon a data bus 24 from where it is read by the main processor 4 under control of the LDR instruction.
摘要翻译：提供了具有主处理器4和协处理器26的数据处理系统。当处于调试模式时，向主处理器4和协处理器26提供不同的指令。协处理器26被提供有协处理器调试数据生成指令（MCR），而主处理器4被提供有主处理器数据捕获指令（LDR）。协处理器26通过控制表示数据处理装置2的状态的调试数据来响应MCR指令，数据处理装置2将被放置在数据总线24上，从LDR指令的控制下由主处理器4读取数据总线24。

10. 发明授权

US09288258B2 Communication using integrated circuit interconnect circuitry 有权
标题翻译：使用集成电路互连电路的通信
公开(公告)号：US09288258B2
公开(公告)日：2016-03-15
申请号：US13825190
申请日：2011-10-11
申请人： Timothy Charles Mace , Andrew Christopher Rose
发明人： Timothy Charles Mace , Andrew Christopher Rose
IPC分类号： H04L29/08 , H04L12/40 , H04L12/46 , G06F15/78 , H04L12/701
CPC分类号： H04L67/10 , G06F15/7825 , G06F15/7842 , H04L12/40084 , H04L12/46 , H04L45/00
摘要： An integrated circuit comprising multiple master units and multiple slave units connected via interconnect circuitry utilizes token based node-to-node communication flow management within the interconnect circuitry with a network node requesting a token and receiving a token signal before it asserts its communication signals onto a physical communication link shared between multiple virtual networks.
摘要翻译：包括通过互连电路连接的多个主单元和多个从单元的集成电路在互连电路内使用基于令牌的节点到节点通信流管理，网络节点请求令牌，并在将其通信信号置于物理通信链路在多个虚拟网络之间共享。

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